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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0247-drm-amdgpu-add-picasso-support-for-gfx_v9_0.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.19.8/0247-drm-amdgpu-add-picasso-support-for-gfx_v9_0.patch136
1 files changed, 136 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0247-drm-amdgpu-add-picasso-support-for-gfx_v9_0.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0247-drm-amdgpu-add-picasso-support-for-gfx_v9_0.patch
new file mode 100644
index 00000000..f553ddae
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0247-drm-amdgpu-add-picasso-support-for-gfx_v9_0.patch
@@ -0,0 +1,136 @@
+From cbaddb489b42a476d876702a176219be6af0d124 Mon Sep 17 00:00:00 2001
+From: Likun Gao <Likun.Gao@amd.com>
+Date: Tue, 10 Jul 2018 20:29:12 +0800
+Subject: [PATCH 0247/2940] drm/amdgpu: add picasso support for gfx_v9_0
+
+Add gfx support to picasso
+
+Signed-off-by: Likun Gao <Likun.Gao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 30 ++++++++++++++++++++++++---
+ 1 file changed, 27 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 78666f71b056..d5e7b9880d03 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -80,6 +80,13 @@ MODULE_FIRMWARE("amdgpu/raven_mec.bin");
+ MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
+ MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
+
++MODULE_FIRMWARE("amdgpu/picasso_ce.bin");
++MODULE_FIRMWARE("amdgpu/picasso_pfp.bin");
++MODULE_FIRMWARE("amdgpu/picasso_me.bin");
++MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
++MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
++MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
++
+ static const struct soc15_reg_golden golden_settings_gc_9_0[] =
+ {
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
+@@ -240,6 +247,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
+ #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
+ #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
+ #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
++#define PICASSO_GB_ADDR_CONFIG_GOLDEN 0x24000042
+
+ static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
+ static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
+@@ -279,6 +287,7 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
+ ARRAY_SIZE(golden_settings_gc_9_0_vg20));
+ break;
+ case CHIP_RAVEN:
++ case CHIP_PICASSO:
+ soc15_program_register_sequence(adev,
+ golden_settings_gc_9_1,
+ ARRAY_SIZE(golden_settings_gc_9_1));
+@@ -566,6 +575,9 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
+ case CHIP_RAVEN:
+ chip_name = "raven";
+ break;
++ case CHIP_PICASSO:
++ chip_name = "picasso";
++ break;
+ default:
+ BUG();
+ }
+@@ -1019,7 +1031,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
+ amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+ }
+
+- if (adev->asic_type == CHIP_RAVEN) {
++ if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) {
+ /* TODO: double check the cp_table_size for RV */
+ adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
+ r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
+@@ -1268,6 +1280,14 @@ static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
+ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
+ gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
+ break;
++ case CHIP_PICASSO:
++ adev->gfx.config.max_hw_contexts = 8;
++ adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
++ adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
++ adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
++ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
++ gb_addr_config = PICASSO_GB_ADDR_CONFIG_GOLDEN;
++ break;
+ default:
+ BUG();
+ break;
+@@ -1546,6 +1566,7 @@ static int gfx_v9_0_sw_init(void *handle)
+ case CHIP_VEGA12:
+ case CHIP_VEGA20:
+ case CHIP_RAVEN:
++ case CHIP_PICASSO:
+ adev->gfx.mec.num_mec = 2;
+ break;
+ default:
+@@ -1707,7 +1728,7 @@ static int gfx_v9_0_sw_fini(void *handle)
+ amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
+ &adev->gfx.rlc.clear_state_gpu_addr,
+ (void **)&adev->gfx.rlc.cs_ptr);
+- if (adev->asic_type == CHIP_RAVEN) {
++ if ((adev->asic_type == CHIP_RAVEN) || (adev->asic_type == CHIP_PICASSO)) {
+ amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
+ &adev->gfx.rlc.cp_table_gpu_addr,
+ (void **)&adev->gfx.rlc.cp_table_ptr);
+@@ -2377,7 +2398,7 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
+ return r;
+ }
+
+- if (adev->asic_type == CHIP_RAVEN) {
++ if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO) {
+ if (amdgpu_lbpw != 0)
+ gfx_v9_0_enable_lbpw(adev, true);
+ else
+@@ -3781,6 +3802,7 @@ static int gfx_v9_0_set_powergating_state(void *handle,
+
+ switch (adev->asic_type) {
+ case CHIP_RAVEN:
++ case CHIP_PICASSO:
+ if (!enable) {
+ amdgpu_gfx_off_ctrl(adev, false);
+ cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
+@@ -3835,6 +3857,7 @@ static int gfx_v9_0_set_clockgating_state(void *handle,
+ case CHIP_VEGA12:
+ case CHIP_VEGA20:
+ case CHIP_RAVEN:
++ case CHIP_PICASSO:
+ gfx_v9_0_update_gfx_clock_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ break;
+@@ -4844,6 +4867,7 @@ static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
+ case CHIP_VEGA12:
+ case CHIP_VEGA20:
+ case CHIP_RAVEN:
++ case CHIP_PICASSO:
+ adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
+ break;
+ default:
+--
+2.17.1
+