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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0242-drm-amdgpu-add-soc15-support-for-picasso.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.19.8/0242-drm-amdgpu-add-soc15-support-for-picasso.patch111
1 files changed, 111 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0242-drm-amdgpu-add-soc15-support-for-picasso.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0242-drm-amdgpu-add-soc15-support-for-picasso.patch
new file mode 100644
index 00000000..148b5320
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0242-drm-amdgpu-add-soc15-support-for-picasso.patch
@@ -0,0 +1,111 @@
+From cefd03a721d2dce9fbf10bef2994034641f7e333 Mon Sep 17 00:00:00 2001
+From: Likun Gao <Likun.Gao@amd.com>
+Date: Tue, 10 Jul 2018 20:22:36 +0800
+Subject: [PATCH 0242/2940] drm/amdgpu: add soc15 support for picasso
+
+Add the IP blocks, clock and powergating flags, and common clockgating support.
+
+Signed-off-by: Likun Gao <Likun.Gao@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Kalyan Alle <kalyan.alle@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 ++++++-
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 21 +++++++++++++++++++++
+ include/drm/amd_asic_type.h | 1 +
+ 3 files changed, 28 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 7ac273235cab..77a7294c2740 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -62,6 +62,7 @@
+ MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
+ MODULE_FIRMWARE("amdgpu/vega12_gpu_info.bin");
+ MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
++MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
+
+ #define AMDGPU_RESUME_MS 2000
+
+@@ -1383,6 +1384,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
+ case CHIP_RAVEN:
+ chip_name = "raven";
+ break;
++ case CHIP_PICASSO:
++ chip_name = "picasso";
++ break;
+ }
+
+ snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
+@@ -1508,7 +1512,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
+ case CHIP_VEGA12:
+ case CHIP_VEGA20:
+ case CHIP_RAVEN:
+- if (adev->asic_type == CHIP_RAVEN)
++ case CHIP_PICASSO:
++ if ((adev->asic_type == CHIP_RAVEN) || (adev->asic_type == CHIP_PICASSO))
+ adev->family = AMDGPU_FAMILY_RV;
+ else
+ adev->family = AMDGPU_FAMILY_AI;
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index 29f72e7b785a..a312d937a0d6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -486,6 +486,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
+ case CHIP_VEGA10:
+ case CHIP_VEGA12:
+ case CHIP_RAVEN:
++ case CHIP_PICASSO:
+ vega10_reg_base_init(adev);
+ break;
+ case CHIP_VEGA20:
+@@ -724,6 +725,25 @@ static int soc15_common_early_init(void *handle)
+
+ adev->external_rev_id = 0x1;
+ break;
++ case CHIP_PICASSO:
++ adev->cg_flags = AMD_CG_SUPPORT_GFX_MGLS |
++ AMD_CG_SUPPORT_GFX_CP_LS |
++ AMD_CG_SUPPORT_GFX_3D_CGCG |
++ AMD_CG_SUPPORT_GFX_3D_CGLS |
++ AMD_CG_SUPPORT_GFX_CGCG |
++ AMD_CG_SUPPORT_GFX_CGLS |
++ AMD_CG_SUPPORT_BIF_LS |
++ AMD_CG_SUPPORT_HDP_LS |
++ AMD_CG_SUPPORT_ROM_MGCG |
++ AMD_CG_SUPPORT_MC_MGCG |
++ AMD_CG_SUPPORT_MC_LS |
++ AMD_CG_SUPPORT_SDMA_MGCG |
++ AMD_CG_SUPPORT_SDMA_LS;
++
++ adev->pg_flags = 0;
++
++ adev->external_rev_id = adev->rev_id + 0x41;
++ break;
+ default:
+ /* FIXME: not supported yet */
+ return -EINVAL;
+@@ -924,6 +944,7 @@ static int soc15_common_set_clockgating_state(void *handle,
+ state == AMD_CG_STATE_GATE ? true : false);
+ break;
+ case CHIP_RAVEN:
++ case CHIP_PICASSO:
+ adev->nbio_funcs->update_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE ? true : false);
+ adev->nbio_funcs->update_medium_grain_light_sleep(adev,
+diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h
+index dd63d08cc54e..5644fc679d6f 100644
+--- a/include/drm/amd_asic_type.h
++++ b/include/drm/amd_asic_type.h
+@@ -49,6 +49,7 @@ enum amd_asic_type {
+ CHIP_VEGA12,
+ CHIP_VEGA20,
+ CHIP_RAVEN,
++ CHIP_PICASSO,
+ CHIP_LAST,
+ };
+
+--
+2.17.1
+