diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0193-drm-amdgpu-implement-soft_recovery-for-GFX7.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0193-drm-amdgpu-implement-soft_recovery-for-GFX7.patch | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0193-drm-amdgpu-implement-soft_recovery-for-GFX7.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0193-drm-amdgpu-implement-soft_recovery-for-GFX7.patch new file mode 100644 index 00000000..c5740394 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0193-drm-amdgpu-implement-soft_recovery-for-GFX7.patch @@ -0,0 +1,51 @@ +From 94d73a82ce85c9542b867b99ba3128a80da1010e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Wed, 22 Aug 2018 11:55:23 +0200 +Subject: [PATCH 0193/2940] drm/amdgpu: implement soft_recovery for GFX7 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Try to kill waves on the SQ. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Huang Rui <ray.huang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +index 95452c5a9df6..a15d9c0f233b 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +@@ -4212,6 +4212,18 @@ static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, + amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); + } + ++static void gfx_v7_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) ++{ ++ struct amdgpu_device *adev = ring->adev; ++ uint32_t value = 0; ++ ++ value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); ++ value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); ++ value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); ++ value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); ++ WREG32(mmSQ_CMD, value); ++} ++ + static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address) + { + WREG32(mmSQ_IND_INDEX, +@@ -5088,6 +5100,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { + .pad_ib = amdgpu_ring_generic_pad_ib, + .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl, + .emit_wreg = gfx_v7_0_ring_emit_wreg, ++ .soft_recovery = gfx_v7_0_ring_soft_recovery, + }; + + static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { +-- +2.17.1 + |