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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0155-drm-amdgpu-Set-power-ungate-state-when-suspend-fini.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.19.8/0155-drm-amdgpu-Set-power-ungate-state-when-suspend-fini.patch126
1 files changed, 126 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0155-drm-amdgpu-Set-power-ungate-state-when-suspend-fini.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0155-drm-amdgpu-Set-power-ungate-state-when-suspend-fini.patch
new file mode 100644
index 00000000..723f885c
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0155-drm-amdgpu-Set-power-ungate-state-when-suspend-fini.patch
@@ -0,0 +1,126 @@
+From de372d301c00735b208237180dee462628f94b1a Mon Sep 17 00:00:00 2001
+From: Rex Zhu <Rex.Zhu@amd.com>
+Date: Tue, 14 Aug 2018 16:54:15 +0800
+Subject: [PATCH 0155/2940] drm/amdgpu: Set power ungate state when
+ suspend/fini
+
+Unify to set power ungate state at the begin of suspend/fini.
+Remove the workaround code for gfx off feature in
+amdgpu_device.c.
+
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 11 +++++------
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ----
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 19 ++++++++++++-------
+ 3 files changed, 17 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index c7b4bdf21249..c4e822f808ea 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -1865,6 +1865,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
+ int i, r;
+
+ amdgpu_amdkfd_device_fini(adev);
++
++ amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
+ /* need to disable SMC first */
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (!adev->ip_blocks[i].status.hw)
+@@ -1879,8 +1881,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
+ adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
+- amdgpu_gfx_off_ctrl(adev, false);
+- cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
++
+ r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
+ /* XXX handle errors */
+ if (r) {
+@@ -2003,6 +2004,8 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev)
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_request_full_gpu(adev, false);
+
++ amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
++
+ for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
+ if (!adev->ip_blocks[i].status.valid)
+ continue;
+@@ -2058,10 +2061,6 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
+ DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
+ }
+
+- /* call smu to disable gfx off feature first when suspend */
+- amdgpu_gfx_off_ctrl(adev, false);
+- cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
+-
+ for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
+ if (!adev->ip_blocks[i].status.valid)
+ continue;
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index 5a9534a82d40..fb66c4f3bf9f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -5164,10 +5164,6 @@ static int gfx_v8_0_hw_fini(void *handle)
+ gfx_v8_0_cp_enable(adev, false);
+ gfx_v8_0_rlc_stop(adev);
+
+- amdgpu_device_ip_set_powergating_state(adev,
+- AMD_IP_BLOCK_TYPE_GFX,
+- AMD_PG_STATE_UNGATE);
+-
+ return 0;
+ }
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index 803421099d41..880eba5a6dd0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -3246,9 +3246,6 @@ static int gfx_v9_0_hw_fini(void *handle)
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+ int i;
+
+- amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_GFX,
+- AMD_PG_STATE_UNGATE);
+-
+ amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
+ amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
+
+@@ -3767,6 +3764,10 @@ static int gfx_v9_0_set_powergating_state(void *handle,
+
+ switch (adev->asic_type) {
+ case CHIP_RAVEN:
++ if (!enable) {
++ amdgpu_gfx_off_ctrl(adev, false);
++ cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
++ }
+ if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
+ gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
+ gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
+@@ -3786,12 +3787,16 @@ static int gfx_v9_0_set_powergating_state(void *handle,
+ /* update mgcg state */
+ gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
+
+- /* set gfx off through smu */
+- amdgpu_gfx_off_ctrl(adev, true);
++ if (enable)
++ amdgpu_gfx_off_ctrl(adev, true);
+ break;
+ case CHIP_VEGA12:
+- /* set gfx off through smu */
+- amdgpu_gfx_off_ctrl(adev, true);
++ if (!enable) {
++ amdgpu_gfx_off_ctrl(adev, false);
++ cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
++ } else {
++ amdgpu_gfx_off_ctrl(adev, true);
++ }
+ break;
+ default:
+ break;
+--
+2.17.1
+