diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0102-drm-amdgpu-use-scheduler-load-balancing-for-SDMA-CS.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0102-drm-amdgpu-use-scheduler-load-balancing-for-SDMA-CS.patch | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0102-drm-amdgpu-use-scheduler-load-balancing-for-SDMA-CS.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0102-drm-amdgpu-use-scheduler-load-balancing-for-SDMA-CS.patch new file mode 100644 index 00000000..740cbda6 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0102-drm-amdgpu-use-scheduler-load-balancing-for-SDMA-CS.patch @@ -0,0 +1,74 @@ +From 94f59ad390d4072e466650df44c24f15178e3276 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Fri, 13 Jul 2018 09:12:44 +0200 +Subject: [PATCH 0102/2940] drm/amdgpu: use scheduler load balancing for SDMA + CS +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Start to use the scheduler load balancing for userspace SDMA +command submissions. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Chunming Zhou <david1.zhou@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 25 +++++++++++++++++++++---- + 1 file changed, 21 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +index 02d563cfb4a7..3ff8042b8f89 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +@@ -48,7 +48,8 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, + struct drm_file *filp, + struct amdgpu_ctx *ctx) + { +- unsigned i, j; ++ struct drm_sched_rq *sdma_rqs[AMDGPU_MAX_RINGS]; ++ unsigned i, j, num_sdma_rqs; + int r; + + if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX) +@@ -80,18 +81,34 @@ static int amdgpu_ctx_init(struct amdgpu_device *adev, + ctx->init_priority = priority; + ctx->override_priority = DRM_SCHED_PRIORITY_UNSET; + +- /* create context entity for each ring */ ++ num_sdma_rqs = 0; + for (i = 0; i < adev->num_rings; i++) { + struct amdgpu_ring *ring = adev->rings[i]; + struct drm_sched_rq *rq; + + rq = &ring->sched.sched_rq[priority]; ++ if (ring->funcs->type == AMDGPU_RING_TYPE_SDMA) ++ sdma_rqs[num_sdma_rqs++] = rq; ++ } ++ ++ /* create context entity for each ring */ ++ for (i = 0; i < adev->num_rings; i++) { ++ struct amdgpu_ring *ring = adev->rings[i]; + + if (ring == &adev->gfx.kiq.ring) + continue; + +- r = drm_sched_entity_init(&ctx->rings[i].entity, +- &rq, 1, &ctx->guilty); ++ if (ring->funcs->type == AMDGPU_RING_TYPE_SDMA) { ++ r = drm_sched_entity_init(&ctx->rings[i].entity, ++ sdma_rqs, num_sdma_rqs, ++ &ctx->guilty); ++ } else { ++ struct drm_sched_rq *rq; ++ ++ rq = &ring->sched.sched_rq[priority]; ++ r = drm_sched_entity_init(&ctx->rings[i].entity, ++ &rq, 1, &ctx->guilty); ++ } + if (r) + goto failed; + } +-- +2.17.1 + |