diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0082-drm-amd-powerplay-revise-vega20-PPSMC_MSG_SetSoftMin.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0082-drm-amd-powerplay-revise-vega20-PPSMC_MSG_SetSoftMin.patch | 175 |
1 files changed, 175 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0082-drm-amd-powerplay-revise-vega20-PPSMC_MSG_SetSoftMin.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0082-drm-amd-powerplay-revise-vega20-PPSMC_MSG_SetSoftMin.patch new file mode 100644 index 00000000..adf32ecb --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0082-drm-amd-powerplay-revise-vega20-PPSMC_MSG_SetSoftMin.patch @@ -0,0 +1,175 @@ +From be71e1116f6802c066bc141419702cdee284b69f Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Mon, 21 May 2018 10:24:57 +0800 +Subject: [PATCH 0082/2940] drm/amd/powerplay: revise vega20 + PPSMC_MSG_SetSoftMin/[Max]ByFreq settings + +UVD, VCE and Socclk also need to be taken into consideration when +setting PPSMC_MSG_SetSoftMinByFreq and PPSMC_MSG_SetSoftMaxByFreq. + +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 109 +++++++++++++++--- + 1 file changed, 96 insertions(+), 13 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +index 1e9426fb1bf9..3f769f37e9fb 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +@@ -1485,31 +1485,72 @@ static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr) + { + struct vega20_hwmgr *data = + (struct vega20_hwmgr *)(hwmgr->backend); ++ uint32_t min_freq; + int ret = 0; + +- if (data->smu_features[GNLD_DPM_GFXCLK].enabled) ++ if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { ++ min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level; + PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( + hwmgr, PPSMC_MSG_SetSoftMinByFreq, +- PPCLK_GFXCLK << 16 | +- data->dpm_table.gfx_table.dpm_state.soft_min_level)), ++ (PPCLK_GFXCLK << 16) | (min_freq & 0xffff))), + "Failed to set soft min gfxclk !", + return ret); ++ } + + if (data->smu_features[GNLD_DPM_UCLK].enabled) { ++ min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level; + PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( + hwmgr, PPSMC_MSG_SetSoftMinByFreq, +- PPCLK_UCLK << 16 | +- data->dpm_table.mem_table.dpm_state.soft_min_level)), ++ (PPCLK_UCLK << 16) | (min_freq & 0xffff))), + "Failed to set soft min memclk !", + return ret); ++ ++ min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level; + PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( + hwmgr, PPSMC_MSG_SetHardMinByFreq, +- PPCLK_UCLK << 16 | +- data->dpm_table.mem_table.dpm_state.hard_min_level)), ++ (PPCLK_UCLK << 16) | (min_freq & 0xffff))), + "Failed to set hard min memclk !", + return ret); + } + ++ if (data->smu_features[GNLD_DPM_UVD].enabled) { ++ min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level; ++ ++ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( ++ hwmgr, PPSMC_MSG_SetSoftMinByFreq, ++ (PPCLK_VCLK << 16) | (min_freq & 0xffff))), ++ "Failed to set soft min vclk!", ++ return ret); ++ ++ min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; ++ ++ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( ++ hwmgr, PPSMC_MSG_SetSoftMinByFreq, ++ (PPCLK_DCLK << 16) | (min_freq & 0xffff))), ++ "Failed to set soft min dclk!", ++ return ret); ++ } ++ ++ if (data->smu_features[GNLD_DPM_VCE].enabled) { ++ min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level; ++ ++ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( ++ hwmgr, PPSMC_MSG_SetSoftMinByFreq, ++ (PPCLK_ECLK << 16) | (min_freq & 0xffff))), ++ "Failed to set soft min eclk!", ++ return ret); ++ } ++ ++ if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { ++ min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level; ++ ++ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( ++ hwmgr, PPSMC_MSG_SetSoftMinByFreq, ++ (PPCLK_SOCCLK << 16) | (min_freq & 0xffff))), ++ "Failed to set soft min socclk!", ++ return ret); ++ } ++ + return ret; + } + +@@ -1517,23 +1558,65 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr) + { + struct vega20_hwmgr *data = + (struct vega20_hwmgr *)(hwmgr->backend); ++ uint32_t max_freq; + int ret = 0; + +- if (data->smu_features[GNLD_DPM_GFXCLK].enabled) ++ if (data->smu_features[GNLD_DPM_GFXCLK].enabled) { ++ max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level; ++ + PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( + hwmgr, PPSMC_MSG_SetSoftMaxByFreq, +- PPCLK_GFXCLK << 16 | +- data->dpm_table.gfx_table.dpm_state.soft_max_level)), ++ (PPCLK_GFXCLK << 16) | (max_freq & 0xffff))), + "Failed to set soft max gfxclk!", + return ret); ++ } ++ ++ if (data->smu_features[GNLD_DPM_UCLK].enabled) { ++ max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level; + +- if (data->smu_features[GNLD_DPM_UCLK].enabled) + PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( + hwmgr, PPSMC_MSG_SetSoftMaxByFreq, +- PPCLK_UCLK << 16 | +- data->dpm_table.mem_table.dpm_state.soft_max_level)), ++ (PPCLK_UCLK << 16) | (max_freq & 0xffff))), + "Failed to set soft max memclk!", + return ret); ++ } ++ ++ if (data->smu_features[GNLD_DPM_UVD].enabled) { ++ max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level; ++ ++ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( ++ hwmgr, PPSMC_MSG_SetSoftMaxByFreq, ++ (PPCLK_VCLK << 16) | (max_freq & 0xffff))), ++ "Failed to set soft max vclk!", ++ return ret); ++ ++ max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; ++ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( ++ hwmgr, PPSMC_MSG_SetSoftMaxByFreq, ++ (PPCLK_DCLK << 16) | (max_freq & 0xffff))), ++ "Failed to set soft max dclk!", ++ return ret); ++ } ++ ++ if (data->smu_features[GNLD_DPM_VCE].enabled) { ++ max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level; ++ ++ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( ++ hwmgr, PPSMC_MSG_SetSoftMaxByFreq, ++ (PPCLK_ECLK << 16) | (max_freq & 0xffff))), ++ "Failed to set soft max eclk!", ++ return ret); ++ } ++ ++ if (data->smu_features[GNLD_DPM_SOCCLK].enabled) { ++ max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level; ++ ++ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter( ++ hwmgr, PPSMC_MSG_SetSoftMaxByFreq, ++ (PPCLK_SOCCLK << 16) | (max_freq & 0xffff))), ++ "Failed to set soft max socclk!", ++ return ret); ++ } + + return ret; + } +-- +2.17.1 + |