diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0077-drm-amd-powerplay-export-vega20-stable-pstate-clocks.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0077-drm-amd-powerplay-export-vega20-stable-pstate-clocks.patch | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0077-drm-amd-powerplay-export-vega20-stable-pstate-clocks.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0077-drm-amd-powerplay-export-vega20-stable-pstate-clocks.patch new file mode 100644 index 00000000..8d299f93 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0077-drm-amd-powerplay-export-vega20-stable-pstate-clocks.patch @@ -0,0 +1,62 @@ +From 30683e2553a7b3bfef1718119bc5bf3bf0450353 Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Tue, 8 May 2018 18:23:16 +0800 +Subject: [PATCH 0077/2940] drm/amd/powerplay: export vega20 stable pstate + clocks + +Needed for querying the stable pstate clocks. + +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 26 ++++++++++++++++++- + 1 file changed, 25 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +index 289e3ee2006d..7b6e48a01c75 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +@@ -846,6 +846,25 @@ static int vega20_odn_initialize_default_settings( + return 0; + } + ++static int vega20_populate_umdpstate_clocks( ++ struct pp_hwmgr *hwmgr) ++{ ++ struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend); ++ struct vega20_single_dpm_table *gfx_table = &(data->dpm_table.gfx_table); ++ struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table); ++ ++ hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value; ++ hwmgr->pstate_mclk = mem_table->dpm_levels[0].value; ++ ++ if (gfx_table->count > VEGA20_UMD_PSTATE_GFXCLK_LEVEL && ++ mem_table->count > VEGA20_UMD_PSTATE_MCLK_LEVEL) { ++ hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value; ++ hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value; ++ } ++ ++ return 0; ++} ++ + static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr, + PP_Clock *clock, PPCLK_e clock_select) + { +@@ -992,7 +1011,12 @@ static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr) + "[EnableDPMTasks] Failed to initialize odn settings!", + return result); + +- return result; ++ result = vega20_populate_umdpstate_clocks(hwmgr); ++ PP_ASSERT_WITH_CODE(!result, ++ "[EnableDPMTasks] Failed to populate umdpstate clocks!", ++ return result); ++ ++ return 0; + } + + static uint32_t vega20_find_lowest_dpm_level( +-- +2.17.1 + |