diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.19.8/0062-drm-amdgpu-include-Add-sdma0-1-4.2-register-headerfi.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.19.8/0062-drm-amdgpu-include-Add-sdma0-1-4.2-register-headerfi.patch | 8078 |
1 files changed, 8078 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.19.8/0062-drm-amdgpu-include-Add-sdma0-1-4.2-register-headerfi.patch b/common/recipes-kernel/linux/linux-yocto-4.19.8/0062-drm-amdgpu-include-Add-sdma0-1-4.2-register-headerfi.patch new file mode 100644 index 00000000..4b0f34f9 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.19.8/0062-drm-amdgpu-include-Add-sdma0-1-4.2-register-headerfi.patch @@ -0,0 +1,8078 @@ +From db28f2b56d7546dbb9c42994a8be6dd4fbf91709 Mon Sep 17 00:00:00 2001 +From: Feifei Xu <Feifei.Xu@amd.com> +Date: Wed, 17 Jan 2018 19:42:33 +0800 +Subject: [PATCH 0062/2940] drm/amdgpu/include: Add sdma0/1 4.2 register + headerfiles. (v3) + +These are the System DMA register headers for vega20. + +v2: cleanups (Alex) +v3: add missing licenses (Alex) + +Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> +Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../include/asic_reg/sdma0/sdma0_4_2_offset.h | 1047 ++++++ + .../asic_reg/sdma0/sdma0_4_2_sh_mask.h | 2992 +++++++++++++++++ + .../include/asic_reg/sdma1/sdma1_4_2_offset.h | 1039 ++++++ + .../asic_reg/sdma1/sdma1_4_2_sh_mask.h | 2948 ++++++++++++++++ + 4 files changed, 8026 insertions(+) + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h +new file mode 100644 +index 000000000000..30b2f5df1402 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_offset.h +@@ -0,0 +1,1047 @@ ++/* ++ * Copyright (C) 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _sdma0_4_2_0_OFFSET_HEADER ++#define _sdma0_4_2_0_OFFSET_HEADER ++ ++ ++ ++// addressBlock: sdma0_sdma0dec ++// base address: 0x4980 ++#define mmSDMA0_UCODE_ADDR 0x0000 ++#define mmSDMA0_UCODE_ADDR_BASE_IDX 0 ++#define mmSDMA0_UCODE_DATA 0x0001 ++#define mmSDMA0_UCODE_DATA_BASE_IDX 0 ++#define mmSDMA0_VM_CNTL 0x0004 ++#define mmSDMA0_VM_CNTL_BASE_IDX 0 ++#define mmSDMA0_VM_CTX_LO 0x0005 ++#define mmSDMA0_VM_CTX_LO_BASE_IDX 0 ++#define mmSDMA0_VM_CTX_HI 0x0006 ++#define mmSDMA0_VM_CTX_HI_BASE_IDX 0 ++#define mmSDMA0_ACTIVE_FCN_ID 0x0007 ++#define mmSDMA0_ACTIVE_FCN_ID_BASE_IDX 0 ++#define mmSDMA0_VM_CTX_CNTL 0x0008 ++#define mmSDMA0_VM_CTX_CNTL_BASE_IDX 0 ++#define mmSDMA0_VIRT_RESET_REQ 0x0009 ++#define mmSDMA0_VIRT_RESET_REQ_BASE_IDX 0 ++#define mmSDMA0_VF_ENABLE 0x000a ++#define mmSDMA0_VF_ENABLE_BASE_IDX 0 ++#define mmSDMA0_CONTEXT_REG_TYPE0 0x000b ++#define mmSDMA0_CONTEXT_REG_TYPE0_BASE_IDX 0 ++#define mmSDMA0_CONTEXT_REG_TYPE1 0x000c ++#define mmSDMA0_CONTEXT_REG_TYPE1_BASE_IDX 0 ++#define mmSDMA0_CONTEXT_REG_TYPE2 0x000d ++#define mmSDMA0_CONTEXT_REG_TYPE2_BASE_IDX 0 ++#define mmSDMA0_CONTEXT_REG_TYPE3 0x000e ++#define mmSDMA0_CONTEXT_REG_TYPE3_BASE_IDX 0 ++#define mmSDMA0_PUB_REG_TYPE0 0x000f ++#define mmSDMA0_PUB_REG_TYPE0_BASE_IDX 0 ++#define mmSDMA0_PUB_REG_TYPE1 0x0010 ++#define mmSDMA0_PUB_REG_TYPE1_BASE_IDX 0 ++#define mmSDMA0_PUB_REG_TYPE2 0x0011 ++#define mmSDMA0_PUB_REG_TYPE2_BASE_IDX 0 ++#define mmSDMA0_PUB_REG_TYPE3 0x0012 ++#define mmSDMA0_PUB_REG_TYPE3_BASE_IDX 0 ++#define mmSDMA0_MMHUB_CNTL 0x0013 ++#define mmSDMA0_MMHUB_CNTL_BASE_IDX 0 ++#define mmSDMA0_CONTEXT_GROUP_BOUNDARY 0x0019 ++#define mmSDMA0_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 ++#define mmSDMA0_POWER_CNTL 0x001a ++#define mmSDMA0_POWER_CNTL_BASE_IDX 0 ++#define mmSDMA0_CLK_CTRL 0x001b ++#define mmSDMA0_CLK_CTRL_BASE_IDX 0 ++#define mmSDMA0_CNTL 0x001c ++#define mmSDMA0_CNTL_BASE_IDX 0 ++#define mmSDMA0_CHICKEN_BITS 0x001d ++#define mmSDMA0_CHICKEN_BITS_BASE_IDX 0 ++#define mmSDMA0_GB_ADDR_CONFIG 0x001e ++#define mmSDMA0_GB_ADDR_CONFIG_BASE_IDX 0 ++#define mmSDMA0_GB_ADDR_CONFIG_READ 0x001f ++#define mmSDMA0_GB_ADDR_CONFIG_READ_BASE_IDX 0 ++#define mmSDMA0_RB_RPTR_FETCH_HI 0x0020 ++#define mmSDMA0_RB_RPTR_FETCH_HI_BASE_IDX 0 ++#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 ++#define mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 ++#define mmSDMA0_RB_RPTR_FETCH 0x0022 ++#define mmSDMA0_RB_RPTR_FETCH_BASE_IDX 0 ++#define mmSDMA0_IB_OFFSET_FETCH 0x0023 ++#define mmSDMA0_IB_OFFSET_FETCH_BASE_IDX 0 ++#define mmSDMA0_PROGRAM 0x0024 ++#define mmSDMA0_PROGRAM_BASE_IDX 0 ++#define mmSDMA0_STATUS_REG 0x0025 ++#define mmSDMA0_STATUS_REG_BASE_IDX 0 ++#define mmSDMA0_STATUS1_REG 0x0026 ++#define mmSDMA0_STATUS1_REG_BASE_IDX 0 ++#define mmSDMA0_RD_BURST_CNTL 0x0027 ++#define mmSDMA0_RD_BURST_CNTL_BASE_IDX 0 ++#define mmSDMA0_HBM_PAGE_CONFIG 0x0028 ++#define mmSDMA0_HBM_PAGE_CONFIG_BASE_IDX 0 ++#define mmSDMA0_UCODE_CHECKSUM 0x0029 ++#define mmSDMA0_UCODE_CHECKSUM_BASE_IDX 0 ++#define mmSDMA0_F32_CNTL 0x002a ++#define mmSDMA0_F32_CNTL_BASE_IDX 0 ++#define mmSDMA0_FREEZE 0x002b ++#define mmSDMA0_FREEZE_BASE_IDX 0 ++#define mmSDMA0_PHASE0_QUANTUM 0x002c ++#define mmSDMA0_PHASE0_QUANTUM_BASE_IDX 0 ++#define mmSDMA0_PHASE1_QUANTUM 0x002d ++#define mmSDMA0_PHASE1_QUANTUM_BASE_IDX 0 ++#define mmSDMA_POWER_GATING 0x002e ++#define mmSDMA_POWER_GATING_BASE_IDX 0 ++#define mmSDMA_PGFSM_CONFIG 0x002f ++#define mmSDMA_PGFSM_CONFIG_BASE_IDX 0 ++#define mmSDMA_PGFSM_WRITE 0x0030 ++#define mmSDMA_PGFSM_WRITE_BASE_IDX 0 ++#define mmSDMA_PGFSM_READ 0x0031 ++#define mmSDMA_PGFSM_READ_BASE_IDX 0 ++#define mmSDMA0_EDC_CONFIG 0x0032 ++#define mmSDMA0_EDC_CONFIG_BASE_IDX 0 ++#define mmSDMA0_BA_THRESHOLD 0x0033 ++#define mmSDMA0_BA_THRESHOLD_BASE_IDX 0 ++#define mmSDMA0_ID 0x0034 ++#define mmSDMA0_ID_BASE_IDX 0 ++#define mmSDMA0_VERSION 0x0035 ++#define mmSDMA0_VERSION_BASE_IDX 0 ++#define mmSDMA0_EDC_COUNTER 0x0036 ++#define mmSDMA0_EDC_COUNTER_BASE_IDX 0 ++#define mmSDMA0_EDC_COUNTER_CLEAR 0x0037 ++#define mmSDMA0_EDC_COUNTER_CLEAR_BASE_IDX 0 ++#define mmSDMA0_STATUS2_REG 0x0038 ++#define mmSDMA0_STATUS2_REG_BASE_IDX 0 ++#define mmSDMA0_ATOMIC_CNTL 0x0039 ++#define mmSDMA0_ATOMIC_CNTL_BASE_IDX 0 ++#define mmSDMA0_ATOMIC_PREOP_LO 0x003a ++#define mmSDMA0_ATOMIC_PREOP_LO_BASE_IDX 0 ++#define mmSDMA0_ATOMIC_PREOP_HI 0x003b ++#define mmSDMA0_ATOMIC_PREOP_HI_BASE_IDX 0 ++#define mmSDMA0_UTCL1_CNTL 0x003c ++#define mmSDMA0_UTCL1_CNTL_BASE_IDX 0 ++#define mmSDMA0_UTCL1_WATERMK 0x003d ++#define mmSDMA0_UTCL1_WATERMK_BASE_IDX 0 ++#define mmSDMA0_UTCL1_RD_STATUS 0x003e ++#define mmSDMA0_UTCL1_RD_STATUS_BASE_IDX 0 ++#define mmSDMA0_UTCL1_WR_STATUS 0x003f ++#define mmSDMA0_UTCL1_WR_STATUS_BASE_IDX 0 ++#define mmSDMA0_UTCL1_INV0 0x0040 ++#define mmSDMA0_UTCL1_INV0_BASE_IDX 0 ++#define mmSDMA0_UTCL1_INV1 0x0041 ++#define mmSDMA0_UTCL1_INV1_BASE_IDX 0 ++#define mmSDMA0_UTCL1_INV2 0x0042 ++#define mmSDMA0_UTCL1_INV2_BASE_IDX 0 ++#define mmSDMA0_UTCL1_RD_XNACK0 0x0043 ++#define mmSDMA0_UTCL1_RD_XNACK0_BASE_IDX 0 ++#define mmSDMA0_UTCL1_RD_XNACK1 0x0044 ++#define mmSDMA0_UTCL1_RD_XNACK1_BASE_IDX 0 ++#define mmSDMA0_UTCL1_WR_XNACK0 0x0045 ++#define mmSDMA0_UTCL1_WR_XNACK0_BASE_IDX 0 ++#define mmSDMA0_UTCL1_WR_XNACK1 0x0046 ++#define mmSDMA0_UTCL1_WR_XNACK1_BASE_IDX 0 ++#define mmSDMA0_UTCL1_TIMEOUT 0x0047 ++#define mmSDMA0_UTCL1_TIMEOUT_BASE_IDX 0 ++#define mmSDMA0_UTCL1_PAGE 0x0048 ++#define mmSDMA0_UTCL1_PAGE_BASE_IDX 0 ++#define mmSDMA0_POWER_CNTL_IDLE 0x0049 ++#define mmSDMA0_POWER_CNTL_IDLE_BASE_IDX 0 ++#define mmSDMA0_RELAX_ORDERING_LUT 0x004a ++#define mmSDMA0_RELAX_ORDERING_LUT_BASE_IDX 0 ++#define mmSDMA0_CHICKEN_BITS_2 0x004b ++#define mmSDMA0_CHICKEN_BITS_2_BASE_IDX 0 ++#define mmSDMA0_STATUS3_REG 0x004c ++#define mmSDMA0_STATUS3_REG_BASE_IDX 0 ++#define mmSDMA0_PHYSICAL_ADDR_LO 0x004d ++#define mmSDMA0_PHYSICAL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_PHYSICAL_ADDR_HI 0x004e ++#define mmSDMA0_PHYSICAL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_PHASE2_QUANTUM 0x004f ++#define mmSDMA0_PHASE2_QUANTUM_BASE_IDX 0 ++#define mmSDMA0_ERROR_LOG 0x0050 ++#define mmSDMA0_ERROR_LOG_BASE_IDX 0 ++#define mmSDMA0_PUB_DUMMY_REG0 0x0051 ++#define mmSDMA0_PUB_DUMMY_REG0_BASE_IDX 0 ++#define mmSDMA0_PUB_DUMMY_REG1 0x0052 ++#define mmSDMA0_PUB_DUMMY_REG1_BASE_IDX 0 ++#define mmSDMA0_PUB_DUMMY_REG2 0x0053 ++#define mmSDMA0_PUB_DUMMY_REG2_BASE_IDX 0 ++#define mmSDMA0_PUB_DUMMY_REG3 0x0054 ++#define mmSDMA0_PUB_DUMMY_REG3_BASE_IDX 0 ++#define mmSDMA0_F32_COUNTER 0x0055 ++#define mmSDMA0_F32_COUNTER_BASE_IDX 0 ++#define mmSDMA0_PERFMON_CNTL 0x0057 ++#define mmSDMA0_PERFMON_CNTL_BASE_IDX 0 ++#define mmSDMA0_PERFCOUNTER0_RESULT 0x0058 ++#define mmSDMA0_PERFCOUNTER0_RESULT_BASE_IDX 0 ++#define mmSDMA0_PERFCOUNTER1_RESULT 0x0059 ++#define mmSDMA0_PERFCOUNTER1_RESULT_BASE_IDX 0 ++#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE 0x005a ++#define mmSDMA0_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 ++#define mmSDMA0_CRD_CNTL 0x005b ++#define mmSDMA0_CRD_CNTL_BASE_IDX 0 ++#define mmSDMA0_GPU_IOV_VIOLATION_LOG 0x005d ++#define mmSDMA0_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 ++#define mmSDMA0_ULV_CNTL 0x005e ++#define mmSDMA0_ULV_CNTL_BASE_IDX 0 ++#define mmSDMA0_EA_DBIT_ADDR_DATA 0x0060 ++#define mmSDMA0_EA_DBIT_ADDR_DATA_BASE_IDX 0 ++#define mmSDMA0_EA_DBIT_ADDR_INDEX 0x0061 ++#define mmSDMA0_EA_DBIT_ADDR_INDEX_BASE_IDX 0 ++#define mmSDMA0_GFX_RB_CNTL 0x0080 ++#define mmSDMA0_GFX_RB_CNTL_BASE_IDX 0 ++#define mmSDMA0_GFX_RB_BASE 0x0081 ++#define mmSDMA0_GFX_RB_BASE_BASE_IDX 0 ++#define mmSDMA0_GFX_RB_BASE_HI 0x0082 ++#define mmSDMA0_GFX_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_GFX_RB_RPTR 0x0083 ++#define mmSDMA0_GFX_RB_RPTR_BASE_IDX 0 ++#define mmSDMA0_GFX_RB_RPTR_HI 0x0084 ++#define mmSDMA0_GFX_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA0_GFX_RB_WPTR 0x0085 ++#define mmSDMA0_GFX_RB_WPTR_BASE_IDX 0 ++#define mmSDMA0_GFX_RB_WPTR_HI 0x0086 ++#define mmSDMA0_GFX_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL 0x0087 ++#define mmSDMA0_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA0_GFX_RB_RPTR_ADDR_HI 0x0088 ++#define mmSDMA0_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_GFX_RB_RPTR_ADDR_LO 0x0089 ++#define mmSDMA0_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_GFX_IB_CNTL 0x008a ++#define mmSDMA0_GFX_IB_CNTL_BASE_IDX 0 ++#define mmSDMA0_GFX_IB_RPTR 0x008b ++#define mmSDMA0_GFX_IB_RPTR_BASE_IDX 0 ++#define mmSDMA0_GFX_IB_OFFSET 0x008c ++#define mmSDMA0_GFX_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA0_GFX_IB_BASE_LO 0x008d ++#define mmSDMA0_GFX_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA0_GFX_IB_BASE_HI 0x008e ++#define mmSDMA0_GFX_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_GFX_IB_SIZE 0x008f ++#define mmSDMA0_GFX_IB_SIZE_BASE_IDX 0 ++#define mmSDMA0_GFX_SKIP_CNTL 0x0090 ++#define mmSDMA0_GFX_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA0_GFX_CONTEXT_STATUS 0x0091 ++#define mmSDMA0_GFX_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA0_GFX_DOORBELL 0x0092 ++#define mmSDMA0_GFX_DOORBELL_BASE_IDX 0 ++#define mmSDMA0_GFX_CONTEXT_CNTL 0x0093 ++#define mmSDMA0_GFX_CONTEXT_CNTL_BASE_IDX 0 ++#define mmSDMA0_GFX_STATUS 0x00a8 ++#define mmSDMA0_GFX_STATUS_BASE_IDX 0 ++#define mmSDMA0_GFX_DOORBELL_LOG 0x00a9 ++#define mmSDMA0_GFX_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA0_GFX_WATERMARK 0x00aa ++#define mmSDMA0_GFX_WATERMARK_BASE_IDX 0 ++#define mmSDMA0_GFX_DOORBELL_OFFSET 0x00ab ++#define mmSDMA0_GFX_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA0_GFX_CSA_ADDR_LO 0x00ac ++#define mmSDMA0_GFX_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_GFX_CSA_ADDR_HI 0x00ad ++#define mmSDMA0_GFX_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_GFX_IB_SUB_REMAIN 0x00af ++#define mmSDMA0_GFX_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA0_GFX_PREEMPT 0x00b0 ++#define mmSDMA0_GFX_PREEMPT_BASE_IDX 0 ++#define mmSDMA0_GFX_DUMMY_REG 0x00b1 ++#define mmSDMA0_GFX_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 ++#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 ++#define mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_GFX_RB_AQL_CNTL 0x00b4 ++#define mmSDMA0_GFX_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA0_GFX_MINOR_PTR_UPDATE 0x00b5 ++#define mmSDMA0_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA0_GFX_MIDCMD_DATA0 0x00c0 ++#define mmSDMA0_GFX_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA0_GFX_MIDCMD_DATA1 0x00c1 ++#define mmSDMA0_GFX_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA0_GFX_MIDCMD_DATA2 0x00c2 ++#define mmSDMA0_GFX_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA0_GFX_MIDCMD_DATA3 0x00c3 ++#define mmSDMA0_GFX_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA0_GFX_MIDCMD_DATA4 0x00c4 ++#define mmSDMA0_GFX_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA0_GFX_MIDCMD_DATA5 0x00c5 ++#define mmSDMA0_GFX_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA0_GFX_MIDCMD_DATA6 0x00c6 ++#define mmSDMA0_GFX_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA0_GFX_MIDCMD_DATA7 0x00c7 ++#define mmSDMA0_GFX_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA0_GFX_MIDCMD_DATA8 0x00c8 ++#define mmSDMA0_GFX_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA0_GFX_MIDCMD_CNTL 0x00c9 ++#define mmSDMA0_GFX_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA0_PAGE_RB_CNTL 0x00e0 ++#define mmSDMA0_PAGE_RB_CNTL_BASE_IDX 0 ++#define mmSDMA0_PAGE_RB_BASE 0x00e1 ++#define mmSDMA0_PAGE_RB_BASE_BASE_IDX 0 ++#define mmSDMA0_PAGE_RB_BASE_HI 0x00e2 ++#define mmSDMA0_PAGE_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_PAGE_RB_RPTR 0x00e3 ++#define mmSDMA0_PAGE_RB_RPTR_BASE_IDX 0 ++#define mmSDMA0_PAGE_RB_RPTR_HI 0x00e4 ++#define mmSDMA0_PAGE_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA0_PAGE_RB_WPTR 0x00e5 ++#define mmSDMA0_PAGE_RB_WPTR_BASE_IDX 0 ++#define mmSDMA0_PAGE_RB_WPTR_HI 0x00e6 ++#define mmSDMA0_PAGE_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL 0x00e7 ++#define mmSDMA0_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI 0x00e8 ++#define mmSDMA0_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO 0x00e9 ++#define mmSDMA0_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_PAGE_IB_CNTL 0x00ea ++#define mmSDMA0_PAGE_IB_CNTL_BASE_IDX 0 ++#define mmSDMA0_PAGE_IB_RPTR 0x00eb ++#define mmSDMA0_PAGE_IB_RPTR_BASE_IDX 0 ++#define mmSDMA0_PAGE_IB_OFFSET 0x00ec ++#define mmSDMA0_PAGE_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA0_PAGE_IB_BASE_LO 0x00ed ++#define mmSDMA0_PAGE_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA0_PAGE_IB_BASE_HI 0x00ee ++#define mmSDMA0_PAGE_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_PAGE_IB_SIZE 0x00ef ++#define mmSDMA0_PAGE_IB_SIZE_BASE_IDX 0 ++#define mmSDMA0_PAGE_SKIP_CNTL 0x00f0 ++#define mmSDMA0_PAGE_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA0_PAGE_CONTEXT_STATUS 0x00f1 ++#define mmSDMA0_PAGE_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA0_PAGE_DOORBELL 0x00f2 ++#define mmSDMA0_PAGE_DOORBELL_BASE_IDX 0 ++#define mmSDMA0_PAGE_STATUS 0x0108 ++#define mmSDMA0_PAGE_STATUS_BASE_IDX 0 ++#define mmSDMA0_PAGE_DOORBELL_LOG 0x0109 ++#define mmSDMA0_PAGE_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA0_PAGE_WATERMARK 0x010a ++#define mmSDMA0_PAGE_WATERMARK_BASE_IDX 0 ++#define mmSDMA0_PAGE_DOORBELL_OFFSET 0x010b ++#define mmSDMA0_PAGE_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA0_PAGE_CSA_ADDR_LO 0x010c ++#define mmSDMA0_PAGE_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_PAGE_CSA_ADDR_HI 0x010d ++#define mmSDMA0_PAGE_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_PAGE_IB_SUB_REMAIN 0x010f ++#define mmSDMA0_PAGE_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA0_PAGE_PREEMPT 0x0110 ++#define mmSDMA0_PAGE_PREEMPT_BASE_IDX 0 ++#define mmSDMA0_PAGE_DUMMY_REG 0x0111 ++#define mmSDMA0_PAGE_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 ++#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 ++#define mmSDMA0_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_PAGE_RB_AQL_CNTL 0x0114 ++#define mmSDMA0_PAGE_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA0_PAGE_MINOR_PTR_UPDATE 0x0115 ++#define mmSDMA0_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA0_PAGE_MIDCMD_DATA0 0x0120 ++#define mmSDMA0_PAGE_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA0_PAGE_MIDCMD_DATA1 0x0121 ++#define mmSDMA0_PAGE_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA0_PAGE_MIDCMD_DATA2 0x0122 ++#define mmSDMA0_PAGE_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA0_PAGE_MIDCMD_DATA3 0x0123 ++#define mmSDMA0_PAGE_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA0_PAGE_MIDCMD_DATA4 0x0124 ++#define mmSDMA0_PAGE_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA0_PAGE_MIDCMD_DATA5 0x0125 ++#define mmSDMA0_PAGE_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA0_PAGE_MIDCMD_DATA6 0x0126 ++#define mmSDMA0_PAGE_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA0_PAGE_MIDCMD_DATA7 0x0127 ++#define mmSDMA0_PAGE_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA0_PAGE_MIDCMD_DATA8 0x0128 ++#define mmSDMA0_PAGE_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA0_PAGE_MIDCMD_CNTL 0x0129 ++#define mmSDMA0_PAGE_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC0_RB_CNTL 0x0140 ++#define mmSDMA0_RLC0_RB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC0_RB_BASE 0x0141 ++#define mmSDMA0_RLC0_RB_BASE_BASE_IDX 0 ++#define mmSDMA0_RLC0_RB_BASE_HI 0x0142 ++#define mmSDMA0_RLC0_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC0_RB_RPTR 0x0143 ++#define mmSDMA0_RLC0_RB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC0_RB_RPTR_HI 0x0144 ++#define mmSDMA0_RLC0_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC0_RB_WPTR 0x0145 ++#define mmSDMA0_RLC0_RB_WPTR_BASE_IDX 0 ++#define mmSDMA0_RLC0_RB_WPTR_HI 0x0146 ++#define mmSDMA0_RLC0_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147 ++#define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI 0x0148 ++#define mmSDMA0_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO 0x0149 ++#define mmSDMA0_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC0_IB_CNTL 0x014a ++#define mmSDMA0_RLC0_IB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC0_IB_RPTR 0x014b ++#define mmSDMA0_RLC0_IB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC0_IB_OFFSET 0x014c ++#define mmSDMA0_RLC0_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC0_IB_BASE_LO 0x014d ++#define mmSDMA0_RLC0_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA0_RLC0_IB_BASE_HI 0x014e ++#define mmSDMA0_RLC0_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC0_IB_SIZE 0x014f ++#define mmSDMA0_RLC0_IB_SIZE_BASE_IDX 0 ++#define mmSDMA0_RLC0_SKIP_CNTL 0x0150 ++#define mmSDMA0_RLC0_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC0_CONTEXT_STATUS 0x0151 ++#define mmSDMA0_RLC0_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC0_DOORBELL 0x0152 ++#define mmSDMA0_RLC0_DOORBELL_BASE_IDX 0 ++#define mmSDMA0_RLC0_STATUS 0x0168 ++#define mmSDMA0_RLC0_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC0_DOORBELL_LOG 0x0169 ++#define mmSDMA0_RLC0_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA0_RLC0_WATERMARK 0x016a ++#define mmSDMA0_RLC0_WATERMARK_BASE_IDX 0 ++#define mmSDMA0_RLC0_DOORBELL_OFFSET 0x016b ++#define mmSDMA0_RLC0_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC0_CSA_ADDR_LO 0x016c ++#define mmSDMA0_RLC0_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC0_CSA_ADDR_HI 0x016d ++#define mmSDMA0_RLC0_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC0_IB_SUB_REMAIN 0x016f ++#define mmSDMA0_RLC0_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA0_RLC0_PREEMPT 0x0170 ++#define mmSDMA0_RLC0_PREEMPT_BASE_IDX 0 ++#define mmSDMA0_RLC0_DUMMY_REG 0x0171 ++#define mmSDMA0_RLC0_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 ++#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 ++#define mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC0_RB_AQL_CNTL 0x0174 ++#define mmSDMA0_RLC0_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC0_MINOR_PTR_UPDATE 0x0175 ++#define mmSDMA0_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA0_RLC0_MIDCMD_DATA0 0x0180 ++#define mmSDMA0_RLC0_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA0_RLC0_MIDCMD_DATA1 0x0181 ++#define mmSDMA0_RLC0_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA0_RLC0_MIDCMD_DATA2 0x0182 ++#define mmSDMA0_RLC0_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA0_RLC0_MIDCMD_DATA3 0x0183 ++#define mmSDMA0_RLC0_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA0_RLC0_MIDCMD_DATA4 0x0184 ++#define mmSDMA0_RLC0_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA0_RLC0_MIDCMD_DATA5 0x0185 ++#define mmSDMA0_RLC0_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA0_RLC0_MIDCMD_DATA6 0x0186 ++#define mmSDMA0_RLC0_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA0_RLC0_MIDCMD_DATA7 0x0187 ++#define mmSDMA0_RLC0_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA0_RLC0_MIDCMD_DATA8 0x0188 ++#define mmSDMA0_RLC0_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA0_RLC0_MIDCMD_CNTL 0x0189 ++#define mmSDMA0_RLC0_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC1_RB_CNTL 0x01a0 ++#define mmSDMA0_RLC1_RB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC1_RB_BASE 0x01a1 ++#define mmSDMA0_RLC1_RB_BASE_BASE_IDX 0 ++#define mmSDMA0_RLC1_RB_BASE_HI 0x01a2 ++#define mmSDMA0_RLC1_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC1_RB_RPTR 0x01a3 ++#define mmSDMA0_RLC1_RB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC1_RB_RPTR_HI 0x01a4 ++#define mmSDMA0_RLC1_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC1_RB_WPTR 0x01a5 ++#define mmSDMA0_RLC1_RB_WPTR_BASE_IDX 0 ++#define mmSDMA0_RLC1_RB_WPTR_HI 0x01a6 ++#define mmSDMA0_RLC1_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL 0x01a7 ++#define mmSDMA0_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI 0x01a8 ++#define mmSDMA0_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO 0x01a9 ++#define mmSDMA0_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC1_IB_CNTL 0x01aa ++#define mmSDMA0_RLC1_IB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC1_IB_RPTR 0x01ab ++#define mmSDMA0_RLC1_IB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC1_IB_OFFSET 0x01ac ++#define mmSDMA0_RLC1_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC1_IB_BASE_LO 0x01ad ++#define mmSDMA0_RLC1_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA0_RLC1_IB_BASE_HI 0x01ae ++#define mmSDMA0_RLC1_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC1_IB_SIZE 0x01af ++#define mmSDMA0_RLC1_IB_SIZE_BASE_IDX 0 ++#define mmSDMA0_RLC1_SKIP_CNTL 0x01b0 ++#define mmSDMA0_RLC1_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC1_CONTEXT_STATUS 0x01b1 ++#define mmSDMA0_RLC1_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC1_DOORBELL 0x01b2 ++#define mmSDMA0_RLC1_DOORBELL_BASE_IDX 0 ++#define mmSDMA0_RLC1_STATUS 0x01c8 ++#define mmSDMA0_RLC1_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC1_DOORBELL_LOG 0x01c9 ++#define mmSDMA0_RLC1_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA0_RLC1_WATERMARK 0x01ca ++#define mmSDMA0_RLC1_WATERMARK_BASE_IDX 0 ++#define mmSDMA0_RLC1_DOORBELL_OFFSET 0x01cb ++#define mmSDMA0_RLC1_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC1_CSA_ADDR_LO 0x01cc ++#define mmSDMA0_RLC1_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC1_CSA_ADDR_HI 0x01cd ++#define mmSDMA0_RLC1_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC1_IB_SUB_REMAIN 0x01cf ++#define mmSDMA0_RLC1_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA0_RLC1_PREEMPT 0x01d0 ++#define mmSDMA0_RLC1_PREEMPT_BASE_IDX 0 ++#define mmSDMA0_RLC1_DUMMY_REG 0x01d1 ++#define mmSDMA0_RLC1_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 ++#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 ++#define mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC1_RB_AQL_CNTL 0x01d4 ++#define mmSDMA0_RLC1_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC1_MINOR_PTR_UPDATE 0x01d5 ++#define mmSDMA0_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA0_RLC1_MIDCMD_DATA0 0x01e0 ++#define mmSDMA0_RLC1_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA0_RLC1_MIDCMD_DATA1 0x01e1 ++#define mmSDMA0_RLC1_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA0_RLC1_MIDCMD_DATA2 0x01e2 ++#define mmSDMA0_RLC1_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA0_RLC1_MIDCMD_DATA3 0x01e3 ++#define mmSDMA0_RLC1_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA0_RLC1_MIDCMD_DATA4 0x01e4 ++#define mmSDMA0_RLC1_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA0_RLC1_MIDCMD_DATA5 0x01e5 ++#define mmSDMA0_RLC1_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA0_RLC1_MIDCMD_DATA6 0x01e6 ++#define mmSDMA0_RLC1_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA0_RLC1_MIDCMD_DATA7 0x01e7 ++#define mmSDMA0_RLC1_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA0_RLC1_MIDCMD_DATA8 0x01e8 ++#define mmSDMA0_RLC1_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA0_RLC1_MIDCMD_CNTL 0x01e9 ++#define mmSDMA0_RLC1_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC2_RB_CNTL 0x0200 ++#define mmSDMA0_RLC2_RB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC2_RB_BASE 0x0201 ++#define mmSDMA0_RLC2_RB_BASE_BASE_IDX 0 ++#define mmSDMA0_RLC2_RB_BASE_HI 0x0202 ++#define mmSDMA0_RLC2_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC2_RB_RPTR 0x0203 ++#define mmSDMA0_RLC2_RB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC2_RB_RPTR_HI 0x0204 ++#define mmSDMA0_RLC2_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC2_RB_WPTR 0x0205 ++#define mmSDMA0_RLC2_RB_WPTR_BASE_IDX 0 ++#define mmSDMA0_RLC2_RB_WPTR_HI 0x0206 ++#define mmSDMA0_RLC2_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL 0x0207 ++#define mmSDMA0_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI 0x0208 ++#define mmSDMA0_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO 0x0209 ++#define mmSDMA0_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC2_IB_CNTL 0x020a ++#define mmSDMA0_RLC2_IB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC2_IB_RPTR 0x020b ++#define mmSDMA0_RLC2_IB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC2_IB_OFFSET 0x020c ++#define mmSDMA0_RLC2_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC2_IB_BASE_LO 0x020d ++#define mmSDMA0_RLC2_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA0_RLC2_IB_BASE_HI 0x020e ++#define mmSDMA0_RLC2_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC2_IB_SIZE 0x020f ++#define mmSDMA0_RLC2_IB_SIZE_BASE_IDX 0 ++#define mmSDMA0_RLC2_SKIP_CNTL 0x0210 ++#define mmSDMA0_RLC2_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC2_CONTEXT_STATUS 0x0211 ++#define mmSDMA0_RLC2_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC2_DOORBELL 0x0212 ++#define mmSDMA0_RLC2_DOORBELL_BASE_IDX 0 ++#define mmSDMA0_RLC2_STATUS 0x0228 ++#define mmSDMA0_RLC2_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC2_DOORBELL_LOG 0x0229 ++#define mmSDMA0_RLC2_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA0_RLC2_WATERMARK 0x022a ++#define mmSDMA0_RLC2_WATERMARK_BASE_IDX 0 ++#define mmSDMA0_RLC2_DOORBELL_OFFSET 0x022b ++#define mmSDMA0_RLC2_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC2_CSA_ADDR_LO 0x022c ++#define mmSDMA0_RLC2_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC2_CSA_ADDR_HI 0x022d ++#define mmSDMA0_RLC2_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC2_IB_SUB_REMAIN 0x022f ++#define mmSDMA0_RLC2_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA0_RLC2_PREEMPT 0x0230 ++#define mmSDMA0_RLC2_PREEMPT_BASE_IDX 0 ++#define mmSDMA0_RLC2_DUMMY_REG 0x0231 ++#define mmSDMA0_RLC2_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI 0x0232 ++#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO 0x0233 ++#define mmSDMA0_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC2_RB_AQL_CNTL 0x0234 ++#define mmSDMA0_RLC2_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC2_MINOR_PTR_UPDATE 0x0235 ++#define mmSDMA0_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA0_RLC2_MIDCMD_DATA0 0x0240 ++#define mmSDMA0_RLC2_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA0_RLC2_MIDCMD_DATA1 0x0241 ++#define mmSDMA0_RLC2_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA0_RLC2_MIDCMD_DATA2 0x0242 ++#define mmSDMA0_RLC2_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA0_RLC2_MIDCMD_DATA3 0x0243 ++#define mmSDMA0_RLC2_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA0_RLC2_MIDCMD_DATA4 0x0244 ++#define mmSDMA0_RLC2_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA0_RLC2_MIDCMD_DATA5 0x0245 ++#define mmSDMA0_RLC2_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA0_RLC2_MIDCMD_DATA6 0x0246 ++#define mmSDMA0_RLC2_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA0_RLC2_MIDCMD_DATA7 0x0247 ++#define mmSDMA0_RLC2_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA0_RLC2_MIDCMD_DATA8 0x0248 ++#define mmSDMA0_RLC2_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA0_RLC2_MIDCMD_CNTL 0x0249 ++#define mmSDMA0_RLC2_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC3_RB_CNTL 0x0260 ++#define mmSDMA0_RLC3_RB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC3_RB_BASE 0x0261 ++#define mmSDMA0_RLC3_RB_BASE_BASE_IDX 0 ++#define mmSDMA0_RLC3_RB_BASE_HI 0x0262 ++#define mmSDMA0_RLC3_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC3_RB_RPTR 0x0263 ++#define mmSDMA0_RLC3_RB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC3_RB_RPTR_HI 0x0264 ++#define mmSDMA0_RLC3_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC3_RB_WPTR 0x0265 ++#define mmSDMA0_RLC3_RB_WPTR_BASE_IDX 0 ++#define mmSDMA0_RLC3_RB_WPTR_HI 0x0266 ++#define mmSDMA0_RLC3_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x0267 ++#define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI 0x0268 ++#define mmSDMA0_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO 0x0269 ++#define mmSDMA0_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC3_IB_CNTL 0x026a ++#define mmSDMA0_RLC3_IB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC3_IB_RPTR 0x026b ++#define mmSDMA0_RLC3_IB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC3_IB_OFFSET 0x026c ++#define mmSDMA0_RLC3_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC3_IB_BASE_LO 0x026d ++#define mmSDMA0_RLC3_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA0_RLC3_IB_BASE_HI 0x026e ++#define mmSDMA0_RLC3_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC3_IB_SIZE 0x026f ++#define mmSDMA0_RLC3_IB_SIZE_BASE_IDX 0 ++#define mmSDMA0_RLC3_SKIP_CNTL 0x0270 ++#define mmSDMA0_RLC3_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC3_CONTEXT_STATUS 0x0271 ++#define mmSDMA0_RLC3_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC3_DOORBELL 0x0272 ++#define mmSDMA0_RLC3_DOORBELL_BASE_IDX 0 ++#define mmSDMA0_RLC3_STATUS 0x0288 ++#define mmSDMA0_RLC3_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC3_DOORBELL_LOG 0x0289 ++#define mmSDMA0_RLC3_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA0_RLC3_WATERMARK 0x028a ++#define mmSDMA0_RLC3_WATERMARK_BASE_IDX 0 ++#define mmSDMA0_RLC3_DOORBELL_OFFSET 0x028b ++#define mmSDMA0_RLC3_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC3_CSA_ADDR_LO 0x028c ++#define mmSDMA0_RLC3_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC3_CSA_ADDR_HI 0x028d ++#define mmSDMA0_RLC3_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC3_IB_SUB_REMAIN 0x028f ++#define mmSDMA0_RLC3_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA0_RLC3_PREEMPT 0x0290 ++#define mmSDMA0_RLC3_PREEMPT_BASE_IDX 0 ++#define mmSDMA0_RLC3_DUMMY_REG 0x0291 ++#define mmSDMA0_RLC3_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI 0x0292 ++#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO 0x0293 ++#define mmSDMA0_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC3_RB_AQL_CNTL 0x0294 ++#define mmSDMA0_RLC3_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC3_MINOR_PTR_UPDATE 0x0295 ++#define mmSDMA0_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA0_RLC3_MIDCMD_DATA0 0x02a0 ++#define mmSDMA0_RLC3_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA0_RLC3_MIDCMD_DATA1 0x02a1 ++#define mmSDMA0_RLC3_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA0_RLC3_MIDCMD_DATA2 0x02a2 ++#define mmSDMA0_RLC3_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA0_RLC3_MIDCMD_DATA3 0x02a3 ++#define mmSDMA0_RLC3_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA0_RLC3_MIDCMD_DATA4 0x02a4 ++#define mmSDMA0_RLC3_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA0_RLC3_MIDCMD_DATA5 0x02a5 ++#define mmSDMA0_RLC3_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA0_RLC3_MIDCMD_DATA6 0x02a6 ++#define mmSDMA0_RLC3_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA0_RLC3_MIDCMD_DATA7 0x02a7 ++#define mmSDMA0_RLC3_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA0_RLC3_MIDCMD_DATA8 0x02a8 ++#define mmSDMA0_RLC3_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA0_RLC3_MIDCMD_CNTL 0x02a9 ++#define mmSDMA0_RLC3_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC4_RB_CNTL 0x02c0 ++#define mmSDMA0_RLC4_RB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC4_RB_BASE 0x02c1 ++#define mmSDMA0_RLC4_RB_BASE_BASE_IDX 0 ++#define mmSDMA0_RLC4_RB_BASE_HI 0x02c2 ++#define mmSDMA0_RLC4_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC4_RB_RPTR 0x02c3 ++#define mmSDMA0_RLC4_RB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC4_RB_RPTR_HI 0x02c4 ++#define mmSDMA0_RLC4_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC4_RB_WPTR 0x02c5 ++#define mmSDMA0_RLC4_RB_WPTR_BASE_IDX 0 ++#define mmSDMA0_RLC4_RB_WPTR_HI 0x02c6 ++#define mmSDMA0_RLC4_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL 0x02c7 ++#define mmSDMA0_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI 0x02c8 ++#define mmSDMA0_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO 0x02c9 ++#define mmSDMA0_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC4_IB_CNTL 0x02ca ++#define mmSDMA0_RLC4_IB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC4_IB_RPTR 0x02cb ++#define mmSDMA0_RLC4_IB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC4_IB_OFFSET 0x02cc ++#define mmSDMA0_RLC4_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC4_IB_BASE_LO 0x02cd ++#define mmSDMA0_RLC4_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA0_RLC4_IB_BASE_HI 0x02ce ++#define mmSDMA0_RLC4_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC4_IB_SIZE 0x02cf ++#define mmSDMA0_RLC4_IB_SIZE_BASE_IDX 0 ++#define mmSDMA0_RLC4_SKIP_CNTL 0x02d0 ++#define mmSDMA0_RLC4_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC4_CONTEXT_STATUS 0x02d1 ++#define mmSDMA0_RLC4_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC4_DOORBELL 0x02d2 ++#define mmSDMA0_RLC4_DOORBELL_BASE_IDX 0 ++#define mmSDMA0_RLC4_STATUS 0x02e8 ++#define mmSDMA0_RLC4_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC4_DOORBELL_LOG 0x02e9 ++#define mmSDMA0_RLC4_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA0_RLC4_WATERMARK 0x02ea ++#define mmSDMA0_RLC4_WATERMARK_BASE_IDX 0 ++#define mmSDMA0_RLC4_DOORBELL_OFFSET 0x02eb ++#define mmSDMA0_RLC4_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC4_CSA_ADDR_LO 0x02ec ++#define mmSDMA0_RLC4_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC4_CSA_ADDR_HI 0x02ed ++#define mmSDMA0_RLC4_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC4_IB_SUB_REMAIN 0x02ef ++#define mmSDMA0_RLC4_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA0_RLC4_PREEMPT 0x02f0 ++#define mmSDMA0_RLC4_PREEMPT_BASE_IDX 0 ++#define mmSDMA0_RLC4_DUMMY_REG 0x02f1 ++#define mmSDMA0_RLC4_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI 0x02f2 ++#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO 0x02f3 ++#define mmSDMA0_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC4_RB_AQL_CNTL 0x02f4 ++#define mmSDMA0_RLC4_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC4_MINOR_PTR_UPDATE 0x02f5 ++#define mmSDMA0_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA0_RLC4_MIDCMD_DATA0 0x0300 ++#define mmSDMA0_RLC4_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA0_RLC4_MIDCMD_DATA1 0x0301 ++#define mmSDMA0_RLC4_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA0_RLC4_MIDCMD_DATA2 0x0302 ++#define mmSDMA0_RLC4_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA0_RLC4_MIDCMD_DATA3 0x0303 ++#define mmSDMA0_RLC4_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA0_RLC4_MIDCMD_DATA4 0x0304 ++#define mmSDMA0_RLC4_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA0_RLC4_MIDCMD_DATA5 0x0305 ++#define mmSDMA0_RLC4_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA0_RLC4_MIDCMD_DATA6 0x0306 ++#define mmSDMA0_RLC4_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA0_RLC4_MIDCMD_DATA7 0x0307 ++#define mmSDMA0_RLC4_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA0_RLC4_MIDCMD_DATA8 0x0308 ++#define mmSDMA0_RLC4_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA0_RLC4_MIDCMD_CNTL 0x0309 ++#define mmSDMA0_RLC4_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC5_RB_CNTL 0x0320 ++#define mmSDMA0_RLC5_RB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC5_RB_BASE 0x0321 ++#define mmSDMA0_RLC5_RB_BASE_BASE_IDX 0 ++#define mmSDMA0_RLC5_RB_BASE_HI 0x0322 ++#define mmSDMA0_RLC5_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC5_RB_RPTR 0x0323 ++#define mmSDMA0_RLC5_RB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC5_RB_RPTR_HI 0x0324 ++#define mmSDMA0_RLC5_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC5_RB_WPTR 0x0325 ++#define mmSDMA0_RLC5_RB_WPTR_BASE_IDX 0 ++#define mmSDMA0_RLC5_RB_WPTR_HI 0x0326 ++#define mmSDMA0_RLC5_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL 0x0327 ++#define mmSDMA0_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI 0x0328 ++#define mmSDMA0_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO 0x0329 ++#define mmSDMA0_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC5_IB_CNTL 0x032a ++#define mmSDMA0_RLC5_IB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC5_IB_RPTR 0x032b ++#define mmSDMA0_RLC5_IB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC5_IB_OFFSET 0x032c ++#define mmSDMA0_RLC5_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC5_IB_BASE_LO 0x032d ++#define mmSDMA0_RLC5_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA0_RLC5_IB_BASE_HI 0x032e ++#define mmSDMA0_RLC5_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC5_IB_SIZE 0x032f ++#define mmSDMA0_RLC5_IB_SIZE_BASE_IDX 0 ++#define mmSDMA0_RLC5_SKIP_CNTL 0x0330 ++#define mmSDMA0_RLC5_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC5_CONTEXT_STATUS 0x0331 ++#define mmSDMA0_RLC5_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC5_DOORBELL 0x0332 ++#define mmSDMA0_RLC5_DOORBELL_BASE_IDX 0 ++#define mmSDMA0_RLC5_STATUS 0x0348 ++#define mmSDMA0_RLC5_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC5_DOORBELL_LOG 0x0349 ++#define mmSDMA0_RLC5_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA0_RLC5_WATERMARK 0x034a ++#define mmSDMA0_RLC5_WATERMARK_BASE_IDX 0 ++#define mmSDMA0_RLC5_DOORBELL_OFFSET 0x034b ++#define mmSDMA0_RLC5_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC5_CSA_ADDR_LO 0x034c ++#define mmSDMA0_RLC5_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC5_CSA_ADDR_HI 0x034d ++#define mmSDMA0_RLC5_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC5_IB_SUB_REMAIN 0x034f ++#define mmSDMA0_RLC5_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA0_RLC5_PREEMPT 0x0350 ++#define mmSDMA0_RLC5_PREEMPT_BASE_IDX 0 ++#define mmSDMA0_RLC5_DUMMY_REG 0x0351 ++#define mmSDMA0_RLC5_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI 0x0352 ++#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO 0x0353 ++#define mmSDMA0_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC5_RB_AQL_CNTL 0x0354 ++#define mmSDMA0_RLC5_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC5_MINOR_PTR_UPDATE 0x0355 ++#define mmSDMA0_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA0_RLC5_MIDCMD_DATA0 0x0360 ++#define mmSDMA0_RLC5_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA0_RLC5_MIDCMD_DATA1 0x0361 ++#define mmSDMA0_RLC5_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA0_RLC5_MIDCMD_DATA2 0x0362 ++#define mmSDMA0_RLC5_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA0_RLC5_MIDCMD_DATA3 0x0363 ++#define mmSDMA0_RLC5_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA0_RLC5_MIDCMD_DATA4 0x0364 ++#define mmSDMA0_RLC5_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA0_RLC5_MIDCMD_DATA5 0x0365 ++#define mmSDMA0_RLC5_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA0_RLC5_MIDCMD_DATA6 0x0366 ++#define mmSDMA0_RLC5_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA0_RLC5_MIDCMD_DATA7 0x0367 ++#define mmSDMA0_RLC5_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA0_RLC5_MIDCMD_DATA8 0x0368 ++#define mmSDMA0_RLC5_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA0_RLC5_MIDCMD_CNTL 0x0369 ++#define mmSDMA0_RLC5_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC6_RB_CNTL 0x0380 ++#define mmSDMA0_RLC6_RB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC6_RB_BASE 0x0381 ++#define mmSDMA0_RLC6_RB_BASE_BASE_IDX 0 ++#define mmSDMA0_RLC6_RB_BASE_HI 0x0382 ++#define mmSDMA0_RLC6_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC6_RB_RPTR 0x0383 ++#define mmSDMA0_RLC6_RB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC6_RB_RPTR_HI 0x0384 ++#define mmSDMA0_RLC6_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC6_RB_WPTR 0x0385 ++#define mmSDMA0_RLC6_RB_WPTR_BASE_IDX 0 ++#define mmSDMA0_RLC6_RB_WPTR_HI 0x0386 ++#define mmSDMA0_RLC6_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL 0x0387 ++#define mmSDMA0_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI 0x0388 ++#define mmSDMA0_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO 0x0389 ++#define mmSDMA0_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC6_IB_CNTL 0x038a ++#define mmSDMA0_RLC6_IB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC6_IB_RPTR 0x038b ++#define mmSDMA0_RLC6_IB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC6_IB_OFFSET 0x038c ++#define mmSDMA0_RLC6_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC6_IB_BASE_LO 0x038d ++#define mmSDMA0_RLC6_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA0_RLC6_IB_BASE_HI 0x038e ++#define mmSDMA0_RLC6_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC6_IB_SIZE 0x038f ++#define mmSDMA0_RLC6_IB_SIZE_BASE_IDX 0 ++#define mmSDMA0_RLC6_SKIP_CNTL 0x0390 ++#define mmSDMA0_RLC6_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC6_CONTEXT_STATUS 0x0391 ++#define mmSDMA0_RLC6_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC6_DOORBELL 0x0392 ++#define mmSDMA0_RLC6_DOORBELL_BASE_IDX 0 ++#define mmSDMA0_RLC6_STATUS 0x03a8 ++#define mmSDMA0_RLC6_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC6_DOORBELL_LOG 0x03a9 ++#define mmSDMA0_RLC6_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA0_RLC6_WATERMARK 0x03aa ++#define mmSDMA0_RLC6_WATERMARK_BASE_IDX 0 ++#define mmSDMA0_RLC6_DOORBELL_OFFSET 0x03ab ++#define mmSDMA0_RLC6_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC6_CSA_ADDR_LO 0x03ac ++#define mmSDMA0_RLC6_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC6_CSA_ADDR_HI 0x03ad ++#define mmSDMA0_RLC6_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC6_IB_SUB_REMAIN 0x03af ++#define mmSDMA0_RLC6_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA0_RLC6_PREEMPT 0x03b0 ++#define mmSDMA0_RLC6_PREEMPT_BASE_IDX 0 ++#define mmSDMA0_RLC6_DUMMY_REG 0x03b1 ++#define mmSDMA0_RLC6_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI 0x03b2 ++#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO 0x03b3 ++#define mmSDMA0_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC6_RB_AQL_CNTL 0x03b4 ++#define mmSDMA0_RLC6_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC6_MINOR_PTR_UPDATE 0x03b5 ++#define mmSDMA0_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA0_RLC6_MIDCMD_DATA0 0x03c0 ++#define mmSDMA0_RLC6_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA0_RLC6_MIDCMD_DATA1 0x03c1 ++#define mmSDMA0_RLC6_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA0_RLC6_MIDCMD_DATA2 0x03c2 ++#define mmSDMA0_RLC6_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA0_RLC6_MIDCMD_DATA3 0x03c3 ++#define mmSDMA0_RLC6_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA0_RLC6_MIDCMD_DATA4 0x03c4 ++#define mmSDMA0_RLC6_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA0_RLC6_MIDCMD_DATA5 0x03c5 ++#define mmSDMA0_RLC6_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA0_RLC6_MIDCMD_DATA6 0x03c6 ++#define mmSDMA0_RLC6_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA0_RLC6_MIDCMD_DATA7 0x03c7 ++#define mmSDMA0_RLC6_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA0_RLC6_MIDCMD_DATA8 0x03c8 ++#define mmSDMA0_RLC6_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA0_RLC6_MIDCMD_CNTL 0x03c9 ++#define mmSDMA0_RLC6_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC7_RB_CNTL 0x03e0 ++#define mmSDMA0_RLC7_RB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC7_RB_BASE 0x03e1 ++#define mmSDMA0_RLC7_RB_BASE_BASE_IDX 0 ++#define mmSDMA0_RLC7_RB_BASE_HI 0x03e2 ++#define mmSDMA0_RLC7_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC7_RB_RPTR 0x03e3 ++#define mmSDMA0_RLC7_RB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC7_RB_RPTR_HI 0x03e4 ++#define mmSDMA0_RLC7_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC7_RB_WPTR 0x03e5 ++#define mmSDMA0_RLC7_RB_WPTR_BASE_IDX 0 ++#define mmSDMA0_RLC7_RB_WPTR_HI 0x03e6 ++#define mmSDMA0_RLC7_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL 0x03e7 ++#define mmSDMA0_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI 0x03e8 ++#define mmSDMA0_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO 0x03e9 ++#define mmSDMA0_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC7_IB_CNTL 0x03ea ++#define mmSDMA0_RLC7_IB_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC7_IB_RPTR 0x03eb ++#define mmSDMA0_RLC7_IB_RPTR_BASE_IDX 0 ++#define mmSDMA0_RLC7_IB_OFFSET 0x03ec ++#define mmSDMA0_RLC7_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC7_IB_BASE_LO 0x03ed ++#define mmSDMA0_RLC7_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA0_RLC7_IB_BASE_HI 0x03ee ++#define mmSDMA0_RLC7_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA0_RLC7_IB_SIZE 0x03ef ++#define mmSDMA0_RLC7_IB_SIZE_BASE_IDX 0 ++#define mmSDMA0_RLC7_SKIP_CNTL 0x03f0 ++#define mmSDMA0_RLC7_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC7_CONTEXT_STATUS 0x03f1 ++#define mmSDMA0_RLC7_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC7_DOORBELL 0x03f2 ++#define mmSDMA0_RLC7_DOORBELL_BASE_IDX 0 ++#define mmSDMA0_RLC7_STATUS 0x0408 ++#define mmSDMA0_RLC7_STATUS_BASE_IDX 0 ++#define mmSDMA0_RLC7_DOORBELL_LOG 0x0409 ++#define mmSDMA0_RLC7_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA0_RLC7_WATERMARK 0x040a ++#define mmSDMA0_RLC7_WATERMARK_BASE_IDX 0 ++#define mmSDMA0_RLC7_DOORBELL_OFFSET 0x040b ++#define mmSDMA0_RLC7_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA0_RLC7_CSA_ADDR_LO 0x040c ++#define mmSDMA0_RLC7_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC7_CSA_ADDR_HI 0x040d ++#define mmSDMA0_RLC7_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC7_IB_SUB_REMAIN 0x040f ++#define mmSDMA0_RLC7_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA0_RLC7_PREEMPT 0x0410 ++#define mmSDMA0_RLC7_PREEMPT_BASE_IDX 0 ++#define mmSDMA0_RLC7_DUMMY_REG 0x0411 ++#define mmSDMA0_RLC7_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI 0x0412 ++#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO 0x0413 ++#define mmSDMA0_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA0_RLC7_RB_AQL_CNTL 0x0414 ++#define mmSDMA0_RLC7_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA0_RLC7_MINOR_PTR_UPDATE 0x0415 ++#define mmSDMA0_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA0_RLC7_MIDCMD_DATA0 0x0420 ++#define mmSDMA0_RLC7_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA0_RLC7_MIDCMD_DATA1 0x0421 ++#define mmSDMA0_RLC7_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA0_RLC7_MIDCMD_DATA2 0x0422 ++#define mmSDMA0_RLC7_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA0_RLC7_MIDCMD_DATA3 0x0423 ++#define mmSDMA0_RLC7_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA0_RLC7_MIDCMD_DATA4 0x0424 ++#define mmSDMA0_RLC7_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA0_RLC7_MIDCMD_DATA5 0x0425 ++#define mmSDMA0_RLC7_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA0_RLC7_MIDCMD_DATA6 0x0426 ++#define mmSDMA0_RLC7_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA0_RLC7_MIDCMD_DATA7 0x0427 ++#define mmSDMA0_RLC7_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA0_RLC7_MIDCMD_DATA8 0x0428 ++#define mmSDMA0_RLC7_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA0_RLC7_MIDCMD_CNTL 0x0429 ++#define mmSDMA0_RLC7_MIDCMD_CNTL_BASE_IDX 0 ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h +new file mode 100644 +index 000000000000..11bfb43833ca +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h +@@ -0,0 +1,2992 @@ ++/* ++ * Copyright (C) 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _sdma0_4_2_0_SH_MASK_HEADER ++#define _sdma0_4_2_0_SH_MASK_HEADER ++ ++ ++// addressBlock: sdma0_sdma0dec ++//SDMA0_UCODE_ADDR ++#define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 ++#define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL ++//SDMA0_UCODE_DATA ++#define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 ++#define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL ++//SDMA0_VM_CNTL ++#define SDMA0_VM_CNTL__CMD__SHIFT 0x0 ++#define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL ++//SDMA0_VM_CTX_LO ++#define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 ++#define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_VM_CTX_HI ++#define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 ++#define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_ACTIVE_FCN_ID ++#define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 ++#define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL ++#define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L ++#define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L ++//SDMA0_VM_CTX_CNTL ++#define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 ++#define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 ++#define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L ++#define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L ++//SDMA0_VIRT_RESET_REQ ++#define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL ++#define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L ++//SDMA0_VF_ENABLE ++#define SDMA0_VF_ENABLE__VF_ENABLE__SHIFT 0x0 ++#define SDMA0_VF_ENABLE__VF_ENABLE_MASK 0x00000001L ++//SDMA0_CONTEXT_REG_TYPE0 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L ++#define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L ++//SDMA0_CONTEXT_REG_TYPE1 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd ++#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 ++#define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L ++#define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L ++#define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L ++#define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L ++//SDMA0_CONTEXT_REG_TYPE2 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 ++#define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L ++#define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L ++#define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L ++//SDMA0_CONTEXT_REG_TYPE3 ++#define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 ++#define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL ++//SDMA0_PUB_REG_TYPE0 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 ++#define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 ++#define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe ++#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf ++#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 ++#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 ++#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d ++#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e ++#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f ++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L ++#define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L ++#define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L ++#define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L ++#define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L ++//SDMA0_PUB_REG_TYPE1 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa ++#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb ++#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc ++#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd ++#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe ++#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf ++#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 ++#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b ++#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c ++#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d ++#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e ++#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f ++#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L ++#define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L ++#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L ++#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L ++#define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L ++#define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L ++//SDMA0_PUB_REG_TYPE2 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa ++#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb ++#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM__SHIFT 0xf ++#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a ++#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b ++#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d ++#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e ++#define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PHASE2_QUANTUM_MASK 0x00008000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L ++#define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L ++#define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L ++//SDMA0_PUB_REG_TYPE3 ++#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 ++#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 ++#define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 ++#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L ++#define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L ++#define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL ++//SDMA0_MMHUB_CNTL ++#define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 ++#define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL ++//SDMA0_CONTEXT_GROUP_BOUNDARY ++#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 ++#define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL ++//SDMA0_POWER_CNTL ++#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 ++#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 ++#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 ++#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 ++#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 ++#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 ++#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa ++#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb ++#define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc ++#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a ++#define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L ++#define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L ++#define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L ++#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L ++#define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L ++#define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L ++#define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L ++#define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L ++#define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L ++#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L ++//SDMA0_CLK_CTRL ++#define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L ++#define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L ++//SDMA0_CNTL ++#define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 ++#define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 ++#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 ++#define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 ++#define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 ++#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 ++#define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 ++#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c ++#define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d ++#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e ++#define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L ++#define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L ++#define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L ++#define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L ++#define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L ++#define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L ++#define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L ++#define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L ++#define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L ++#define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L ++//SDMA0_CHICKEN_BITS ++#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 ++#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 ++#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 ++#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 ++#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa ++#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 ++#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 ++#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 ++#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 ++#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 ++#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a ++#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c ++#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e ++#define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L ++#define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L ++#define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L ++#define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L ++#define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L ++#define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L ++#define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L ++#define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L ++#define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L ++#define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L ++#define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L ++#define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L ++#define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L ++//SDMA0_GB_ADDR_CONFIG ++#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 ++#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 ++#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 ++#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc ++#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 ++#define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L ++#define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L ++#define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L ++#define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L ++#define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L ++//SDMA0_GB_ADDR_CONFIG_READ ++#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 ++#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 ++#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 ++#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc ++#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 ++#define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L ++#define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L ++#define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L ++#define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L ++#define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L ++//SDMA0_RB_RPTR_FETCH_HI ++#define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_SEM_WAIT_FAIL_TIMER_CNTL ++#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 ++#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL ++//SDMA0_RB_RPTR_FETCH ++#define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 ++#define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL ++//SDMA0_IB_OFFSET_FETCH ++#define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 ++#define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL ++//SDMA0_PROGRAM ++#define SDMA0_PROGRAM__STREAM__SHIFT 0x0 ++#define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL ++//SDMA0_STATUS_REG ++#define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 ++#define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 ++#define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 ++#define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 ++#define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 ++#define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 ++#define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 ++#define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 ++#define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 ++#define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 ++#define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa ++#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb ++#define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc ++#define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd ++#define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe ++#define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf ++#define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 ++#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 ++#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 ++#define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 ++#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 ++#define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 ++#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 ++#define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 ++#define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a ++#define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b ++#define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c ++#define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e ++#define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f ++#define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L ++#define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L ++#define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L ++#define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L ++#define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L ++#define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L ++#define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L ++#define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L ++#define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L ++#define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L ++#define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L ++#define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L ++#define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L ++#define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L ++#define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L ++#define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L ++#define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L ++#define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L ++#define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L ++#define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L ++#define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L ++#define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L ++#define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L ++#define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L ++#define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L ++#define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L ++#define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L ++#define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L ++#define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L ++//SDMA0_STATUS1_REG ++#define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 ++#define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 ++#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 ++#define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 ++#define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 ++#define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 ++#define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 ++#define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 ++#define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa ++#define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd ++#define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe ++#define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf ++#define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 ++#define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 ++#define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L ++#define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L ++#define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L ++#define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L ++#define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L ++#define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L ++#define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L ++#define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L ++#define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L ++#define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L ++#define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L ++#define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L ++#define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L ++#define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L ++//SDMA0_RD_BURST_CNTL ++#define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 ++#define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 ++#define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L ++#define SDMA0_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL ++//SDMA0_HBM_PAGE_CONFIG ++#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 ++#define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L ++//SDMA0_UCODE_CHECKSUM ++#define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 ++#define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL ++//SDMA0_F32_CNTL ++#define SDMA0_F32_CNTL__HALT__SHIFT 0x0 ++#define SDMA0_F32_CNTL__STEP__SHIFT 0x1 ++#define SDMA0_F32_CNTL__HALT_MASK 0x00000001L ++#define SDMA0_F32_CNTL__STEP_MASK 0x00000002L ++//SDMA0_FREEZE ++#define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 ++#define SDMA0_FREEZE__FREEZE__SHIFT 0x4 ++#define SDMA0_FREEZE__FROZEN__SHIFT 0x5 ++#define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 ++#define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L ++#define SDMA0_FREEZE__FREEZE_MASK 0x00000010L ++#define SDMA0_FREEZE__FROZEN_MASK 0x00000020L ++#define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L ++//SDMA0_PHASE0_QUANTUM ++#define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 ++#define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 ++#define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e ++#define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL ++#define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L ++#define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L ++//SDMA0_PHASE1_QUANTUM ++#define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 ++#define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 ++#define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e ++#define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL ++#define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L ++#define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L ++//SDMA_POWER_GATING ++#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 ++#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 ++#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 ++#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 ++#define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 ++#define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L ++#define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L ++#define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L ++#define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L ++#define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L ++//SDMA_PGFSM_CONFIG ++#define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 ++#define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 ++#define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 ++#define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa ++#define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb ++#define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc ++#define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd ++#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b ++#define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c ++#define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL ++#define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L ++#define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L ++#define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L ++#define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L ++#define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L ++#define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L ++#define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L ++#define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L ++//SDMA_PGFSM_WRITE ++#define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 ++#define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL ++//SDMA_PGFSM_READ ++#define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 ++#define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL ++//SDMA0_EDC_CONFIG ++#define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 ++#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 ++#define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L ++#define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L ++//SDMA0_BA_THRESHOLD ++#define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 ++#define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 ++#define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL ++#define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L ++//SDMA0_ID ++#define SDMA0_ID__DEVICE_ID__SHIFT 0x0 ++#define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL ++//SDMA0_VERSION ++#define SDMA0_VERSION__MINVER__SHIFT 0x0 ++#define SDMA0_VERSION__MAJVER__SHIFT 0x8 ++#define SDMA0_VERSION__REV__SHIFT 0x10 ++#define SDMA0_VERSION__MINVER_MASK 0x0000007FL ++#define SDMA0_VERSION__MAJVER_MASK 0x00007F00L ++#define SDMA0_VERSION__REV_MASK 0x003F0000L ++//SDMA0_EDC_COUNTER ++#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 ++#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 ++#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 ++#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 ++#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 ++#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 ++#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 ++#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 ++#define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L ++#define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L ++#define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L ++#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L ++#define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L ++#define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L ++#define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L ++#define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L ++#define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L ++//SDMA0_EDC_COUNTER_CLEAR ++#define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 ++#define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L ++//SDMA0_STATUS2_REG ++#define SDMA0_STATUS2_REG__ID__SHIFT 0x0 ++#define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 ++#define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 ++#define SDMA0_STATUS2_REG__ID_MASK 0x00000003L ++#define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL ++#define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L ++//SDMA0_ATOMIC_CNTL ++#define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 ++#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f ++#define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL ++#define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L ++//SDMA0_ATOMIC_PREOP_LO ++#define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 ++#define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL ++//SDMA0_ATOMIC_PREOP_HI ++#define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 ++#define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL ++//SDMA0_UTCL1_CNTL ++#define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 ++#define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 ++#define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb ++#define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe ++#define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 ++#define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d ++#define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L ++#define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL ++#define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L ++#define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L ++#define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L ++#define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L ++//SDMA0_UTCL1_WATERMK ++#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 ++#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 ++#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 ++#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 ++#define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL ++#define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L ++#define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L ++#define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L ++//SDMA0_UTCL1_RD_STATUS ++#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 ++#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 ++#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 ++#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 ++#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 ++#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 ++#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 ++#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 ++#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 ++#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 ++#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa ++#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb ++#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc ++#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd ++#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe ++#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf ++#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 ++#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 ++#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 ++#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 ++#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 ++#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 ++#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 ++#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a ++#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d ++#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e ++#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f ++#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L ++#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L ++#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L ++#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L ++#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L ++#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L ++#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L ++#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L ++#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L ++#define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L ++#define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L ++#define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L ++#define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L ++#define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L ++#define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L ++#define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L ++#define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L ++#define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L ++#define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L ++#define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L ++#define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L ++#define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L ++#define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L ++#define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L ++#define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L ++#define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L ++#define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L ++//SDMA0_UTCL1_WR_STATUS ++#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 ++#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 ++#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 ++#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 ++#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 ++#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 ++#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 ++#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 ++#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 ++#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 ++#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa ++#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb ++#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc ++#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd ++#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe ++#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf ++#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 ++#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 ++#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 ++#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 ++#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 ++#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 ++#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 ++#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 ++#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c ++#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d ++#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e ++#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f ++#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L ++#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L ++#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L ++#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L ++#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L ++#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L ++#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L ++#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L ++#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L ++#define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L ++#define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L ++#define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L ++#define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L ++#define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L ++#define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L ++#define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L ++#define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L ++#define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L ++#define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L ++#define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L ++#define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L ++#define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L ++#define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L ++#define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L ++#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L ++#define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L ++#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L ++#define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L ++//SDMA0_UTCL1_INV0 ++#define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 ++#define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 ++#define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 ++#define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 ++#define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 ++#define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 ++#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 ++#define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 ++#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 ++#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 ++#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa ++#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb ++#define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc ++#define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c ++#define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L ++#define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L ++#define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L ++#define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L ++#define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L ++#define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L ++#define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L ++#define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L ++#define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L ++#define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L ++#define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L ++#define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L ++#define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L ++#define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L ++//SDMA0_UTCL1_INV1 ++#define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 ++#define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL ++//SDMA0_UTCL1_INV2 ++#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 ++#define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL ++//SDMA0_UTCL1_RD_XNACK0 ++#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 ++#define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL ++//SDMA0_UTCL1_RD_XNACK1 ++#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 ++#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 ++#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 ++#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a ++#define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL ++#define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L ++#define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L ++#define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L ++//SDMA0_UTCL1_WR_XNACK0 ++#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 ++#define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL ++//SDMA0_UTCL1_WR_XNACK1 ++#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 ++#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 ++#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 ++#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a ++#define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL ++#define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L ++#define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L ++#define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L ++//SDMA0_UTCL1_TIMEOUT ++#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 ++#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 ++#define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL ++#define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L ++//SDMA0_UTCL1_PAGE ++#define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 ++#define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 ++#define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 ++#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 ++#define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L ++#define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL ++#define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L ++#define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L ++//SDMA0_POWER_CNTL_IDLE ++#define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 ++#define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 ++#define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 ++#define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL ++#define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L ++#define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L ++//SDMA0_RELAX_ORDERING_LUT ++#define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 ++#define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 ++#define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 ++#define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 ++#define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 ++#define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 ++#define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 ++#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 ++#define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 ++#define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa ++#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb ++#define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc ++#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd ++#define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe ++#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b ++#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c ++#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d ++#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e ++#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f ++#define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L ++#define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L ++#define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L ++#define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L ++#define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L ++#define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L ++#define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L ++#define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L ++#define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L ++#define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L ++#define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L ++#define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L ++#define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L ++#define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L ++#define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L ++#define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L ++#define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L ++#define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L ++#define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L ++//SDMA0_CHICKEN_BITS_2 ++#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 ++#define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL ++//SDMA0_STATUS3_REG ++#define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 ++#define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 ++#define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 ++#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 ++#define SDMA0_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 ++#define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL ++#define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L ++#define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L ++#define SDMA0_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L ++#define SDMA0_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L ++//SDMA0_PHYSICAL_ADDR_LO ++#define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 ++#define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 ++#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 ++#define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc ++#define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L ++#define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L ++#define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L ++#define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L ++//SDMA0_PHYSICAL_ADDR_HI ++#define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL ++//SDMA0_PHASE2_QUANTUM ++#define SDMA0_PHASE2_QUANTUM__UNIT__SHIFT 0x0 ++#define SDMA0_PHASE2_QUANTUM__VALUE__SHIFT 0x8 ++#define SDMA0_PHASE2_QUANTUM__PREFER__SHIFT 0x1e ++#define SDMA0_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL ++#define SDMA0_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L ++#define SDMA0_PHASE2_QUANTUM__PREFER_MASK 0x40000000L ++//SDMA0_ERROR_LOG ++#define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 ++#define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 ++#define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL ++#define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L ++//SDMA0_PUB_DUMMY_REG0 ++#define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 ++#define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL ++//SDMA0_PUB_DUMMY_REG1 ++#define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 ++#define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL ++//SDMA0_PUB_DUMMY_REG2 ++#define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 ++#define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL ++//SDMA0_PUB_DUMMY_REG3 ++#define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 ++#define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL ++//SDMA0_F32_COUNTER ++#define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 ++#define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL ++//SDMA0_PERFMON_CNTL ++#define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 ++#define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 ++#define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 ++#define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa ++#define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb ++#define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc ++#define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L ++#define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L ++#define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL ++#define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L ++#define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L ++#define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L ++//SDMA0_PERFCOUNTER0_RESULT ++#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 ++#define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL ++//SDMA0_PERFCOUNTER1_RESULT ++#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 ++#define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL ++//SDMA0_PERFCOUNTER_TAG_DELAY_RANGE ++#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 ++#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe ++#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c ++#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL ++#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L ++#define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L ++//SDMA0_CRD_CNTL ++#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 ++#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd ++#define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L ++#define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L ++//SDMA0_GPU_IOV_VIOLATION_LOG ++#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 ++#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 ++#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 ++#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 ++#define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 ++#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 ++#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 ++#define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L ++#define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L ++#define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL ++#define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L ++#define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L ++#define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L ++#define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L ++//SDMA0_ULV_CNTL ++#define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 ++#define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b ++#define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c ++#define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d ++#define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e ++#define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f ++#define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL ++#define SDMA0_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L ++#define SDMA0_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L ++#define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L ++#define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L ++#define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L ++//SDMA0_EA_DBIT_ADDR_DATA ++#define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 ++#define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL ++//SDMA0_EA_DBIT_ADDR_INDEX ++#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 ++#define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L ++//SDMA0_GFX_RB_CNTL ++#define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA0_GFX_RB_BASE ++#define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_GFX_RB_BASE_HI ++#define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA0_GFX_RB_RPTR ++#define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_GFX_RB_RPTR_HI ++#define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_GFX_RB_WPTR ++#define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_GFX_RB_WPTR_HI ++#define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_GFX_RB_WPTR_POLL_CNTL ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA0_GFX_RB_RPTR_ADDR_HI ++#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_GFX_RB_RPTR_ADDR_LO ++#define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_GFX_IB_CNTL ++#define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA0_GFX_IB_RPTR ++#define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA0_GFX_IB_OFFSET ++#define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA0_GFX_IB_BASE_LO ++#define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA0_GFX_IB_BASE_HI ++#define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_GFX_IB_SIZE ++#define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA0_GFX_SKIP_CNTL ++#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA0_GFX_CONTEXT_STATUS ++#define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA0_GFX_DOORBELL ++#define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA0_GFX_CONTEXT_CNTL ++#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 ++#define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L ++//SDMA0_GFX_STATUS ++#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA0_GFX_DOORBELL_LOG ++#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA0_GFX_WATERMARK ++#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA0_GFX_DOORBELL_OFFSET ++#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA0_GFX_CSA_ADDR_LO ++#define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_GFX_CSA_ADDR_HI ++#define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_GFX_IB_SUB_REMAIN ++#define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA0_GFX_PREEMPT ++#define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA0_GFX_DUMMY_REG ++#define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA0_GFX_RB_WPTR_POLL_ADDR_HI ++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_GFX_RB_WPTR_POLL_ADDR_LO ++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_GFX_RB_AQL_CNTL ++#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA0_GFX_MINOR_PTR_UPDATE ++#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA0_GFX_MIDCMD_DATA0 ++#define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA0_GFX_MIDCMD_DATA1 ++#define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA0_GFX_MIDCMD_DATA2 ++#define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA0_GFX_MIDCMD_DATA3 ++#define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA0_GFX_MIDCMD_DATA4 ++#define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA0_GFX_MIDCMD_DATA5 ++#define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA0_GFX_MIDCMD_DATA6 ++#define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA0_GFX_MIDCMD_DATA7 ++#define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA0_GFX_MIDCMD_DATA8 ++#define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA0_GFX_MIDCMD_CNTL ++#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA0_PAGE_RB_CNTL ++#define SDMA0_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA0_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA0_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA0_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA0_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA0_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA0_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA0_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA0_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA0_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA0_PAGE_RB_BASE ++#define SDMA0_PAGE_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA0_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_RB_BASE_HI ++#define SDMA0_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA0_PAGE_RB_RPTR ++#define SDMA0_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_RB_RPTR_HI ++#define SDMA0_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_RB_WPTR ++#define SDMA0_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_RB_WPTR_HI ++#define SDMA0_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_RB_WPTR_POLL_CNTL ++#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA0_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA0_PAGE_RB_RPTR_ADDR_HI ++#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_RB_RPTR_ADDR_LO ++#define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA0_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_PAGE_IB_CNTL ++#define SDMA0_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA0_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA0_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA0_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA0_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA0_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA0_PAGE_IB_RPTR ++#define SDMA0_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA0_PAGE_IB_OFFSET ++#define SDMA0_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA0_PAGE_IB_BASE_LO ++#define SDMA0_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA0_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA0_PAGE_IB_BASE_HI ++#define SDMA0_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_IB_SIZE ++#define SDMA0_PAGE_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA0_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA0_PAGE_SKIP_CNTL ++#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA0_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA0_PAGE_CONTEXT_STATUS ++#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA0_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA0_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA0_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA0_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA0_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA0_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA0_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA0_PAGE_DOORBELL ++#define SDMA0_PAGE_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA0_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA0_PAGE_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA0_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA0_PAGE_STATUS ++#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA0_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA0_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA0_PAGE_DOORBELL_LOG ++#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA0_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA0_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA0_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA0_PAGE_WATERMARK ++#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA0_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA0_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA0_PAGE_DOORBELL_OFFSET ++#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA0_PAGE_CSA_ADDR_LO ++#define SDMA0_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_PAGE_CSA_ADDR_HI ++#define SDMA0_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_IB_SUB_REMAIN ++#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA0_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA0_PAGE_PREEMPT ++#define SDMA0_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA0_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA0_PAGE_DUMMY_REG ++#define SDMA0_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA0_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI ++#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO ++#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_PAGE_RB_AQL_CNTL ++#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA0_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA0_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA0_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA0_PAGE_MINOR_PTR_UPDATE ++#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA0_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA0_PAGE_MIDCMD_DATA0 ++#define SDMA0_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA0_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_MIDCMD_DATA1 ++#define SDMA0_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA0_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_MIDCMD_DATA2 ++#define SDMA0_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA0_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_MIDCMD_DATA3 ++#define SDMA0_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA0_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_MIDCMD_DATA4 ++#define SDMA0_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA0_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_MIDCMD_DATA5 ++#define SDMA0_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA0_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_MIDCMD_DATA6 ++#define SDMA0_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA0_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_MIDCMD_DATA7 ++#define SDMA0_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA0_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_MIDCMD_DATA8 ++#define SDMA0_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA0_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA0_PAGE_MIDCMD_CNTL ++#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA0_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA0_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA0_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA0_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA0_RLC0_RB_CNTL ++#define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA0_RLC0_RB_BASE ++#define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_RB_BASE_HI ++#define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA0_RLC0_RB_RPTR ++#define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_RB_RPTR_HI ++#define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_RB_WPTR ++#define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_RB_WPTR_HI ++#define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_RB_WPTR_POLL_CNTL ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA0_RLC0_RB_RPTR_ADDR_HI ++#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_RB_RPTR_ADDR_LO ++#define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC0_IB_CNTL ++#define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA0_RLC0_IB_RPTR ++#define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC0_IB_OFFSET ++#define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC0_IB_BASE_LO ++#define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA0_RLC0_IB_BASE_HI ++#define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_IB_SIZE ++#define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC0_SKIP_CNTL ++#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA0_RLC0_CONTEXT_STATUS ++#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA0_RLC0_DOORBELL ++#define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA0_RLC0_STATUS ++#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA0_RLC0_DOORBELL_LOG ++#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA0_RLC0_WATERMARK ++#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA0_RLC0_DOORBELL_OFFSET ++#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA0_RLC0_CSA_ADDR_LO ++#define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC0_CSA_ADDR_HI ++#define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_IB_SUB_REMAIN ++#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC0_PREEMPT ++#define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA0_RLC0_DUMMY_REG ++#define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI ++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO ++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC0_RB_AQL_CNTL ++#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA0_RLC0_MINOR_PTR_UPDATE ++#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA0_RLC0_MIDCMD_DATA0 ++#define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_MIDCMD_DATA1 ++#define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_MIDCMD_DATA2 ++#define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_MIDCMD_DATA3 ++#define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_MIDCMD_DATA4 ++#define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_MIDCMD_DATA5 ++#define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_MIDCMD_DATA6 ++#define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_MIDCMD_DATA7 ++#define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_MIDCMD_DATA8 ++#define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA0_RLC0_MIDCMD_CNTL ++#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA0_RLC1_RB_CNTL ++#define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA0_RLC1_RB_BASE ++#define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_RB_BASE_HI ++#define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA0_RLC1_RB_RPTR ++#define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_RB_RPTR_HI ++#define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_RB_WPTR ++#define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_RB_WPTR_HI ++#define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_RB_WPTR_POLL_CNTL ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA0_RLC1_RB_RPTR_ADDR_HI ++#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_RB_RPTR_ADDR_LO ++#define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC1_IB_CNTL ++#define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA0_RLC1_IB_RPTR ++#define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC1_IB_OFFSET ++#define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC1_IB_BASE_LO ++#define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA0_RLC1_IB_BASE_HI ++#define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_IB_SIZE ++#define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC1_SKIP_CNTL ++#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA0_RLC1_CONTEXT_STATUS ++#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA0_RLC1_DOORBELL ++#define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA0_RLC1_STATUS ++#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA0_RLC1_DOORBELL_LOG ++#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA0_RLC1_WATERMARK ++#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA0_RLC1_DOORBELL_OFFSET ++#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA0_RLC1_CSA_ADDR_LO ++#define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC1_CSA_ADDR_HI ++#define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_IB_SUB_REMAIN ++#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC1_PREEMPT ++#define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA0_RLC1_DUMMY_REG ++#define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI ++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO ++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC1_RB_AQL_CNTL ++#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA0_RLC1_MINOR_PTR_UPDATE ++#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA0_RLC1_MIDCMD_DATA0 ++#define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_MIDCMD_DATA1 ++#define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_MIDCMD_DATA2 ++#define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_MIDCMD_DATA3 ++#define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_MIDCMD_DATA4 ++#define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_MIDCMD_DATA5 ++#define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_MIDCMD_DATA6 ++#define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_MIDCMD_DATA7 ++#define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_MIDCMD_DATA8 ++#define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA0_RLC1_MIDCMD_CNTL ++#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA0_RLC2_RB_CNTL ++#define SDMA0_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA0_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA0_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA0_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA0_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA0_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA0_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA0_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA0_RLC2_RB_BASE ++#define SDMA0_RLC2_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA0_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_RB_BASE_HI ++#define SDMA0_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA0_RLC2_RB_RPTR ++#define SDMA0_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_RB_RPTR_HI ++#define SDMA0_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_RB_WPTR ++#define SDMA0_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_RB_WPTR_HI ++#define SDMA0_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_RB_WPTR_POLL_CNTL ++#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA0_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA0_RLC2_RB_RPTR_ADDR_HI ++#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_RB_RPTR_ADDR_LO ++#define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA0_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC2_IB_CNTL ++#define SDMA0_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA0_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA0_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA0_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA0_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA0_RLC2_IB_RPTR ++#define SDMA0_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC2_IB_OFFSET ++#define SDMA0_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC2_IB_BASE_LO ++#define SDMA0_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA0_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA0_RLC2_IB_BASE_HI ++#define SDMA0_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_IB_SIZE ++#define SDMA0_RLC2_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA0_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC2_SKIP_CNTL ++#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA0_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA0_RLC2_CONTEXT_STATUS ++#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA0_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA0_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA0_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA0_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA0_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA0_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA0_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA0_RLC2_DOORBELL ++#define SDMA0_RLC2_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA0_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA0_RLC2_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA0_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA0_RLC2_STATUS ++#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA0_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA0_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA0_RLC2_DOORBELL_LOG ++#define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA0_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA0_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA0_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA0_RLC2_WATERMARK ++#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA0_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA0_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA0_RLC2_DOORBELL_OFFSET ++#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA0_RLC2_CSA_ADDR_LO ++#define SDMA0_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC2_CSA_ADDR_HI ++#define SDMA0_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_IB_SUB_REMAIN ++#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA0_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC2_PREEMPT ++#define SDMA0_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA0_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA0_RLC2_DUMMY_REG ++#define SDMA0_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA0_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI ++#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO ++#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC2_RB_AQL_CNTL ++#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA0_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA0_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA0_RLC2_MINOR_PTR_UPDATE ++#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA0_RLC2_MIDCMD_DATA0 ++#define SDMA0_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA0_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_MIDCMD_DATA1 ++#define SDMA0_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA0_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_MIDCMD_DATA2 ++#define SDMA0_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA0_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_MIDCMD_DATA3 ++#define SDMA0_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA0_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_MIDCMD_DATA4 ++#define SDMA0_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA0_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_MIDCMD_DATA5 ++#define SDMA0_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA0_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_MIDCMD_DATA6 ++#define SDMA0_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA0_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_MIDCMD_DATA7 ++#define SDMA0_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA0_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_MIDCMD_DATA8 ++#define SDMA0_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA0_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA0_RLC2_MIDCMD_CNTL ++#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA0_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA0_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA0_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA0_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA0_RLC3_RB_CNTL ++#define SDMA0_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA0_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA0_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA0_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA0_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA0_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA0_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA0_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA0_RLC3_RB_BASE ++#define SDMA0_RLC3_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA0_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_RB_BASE_HI ++#define SDMA0_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA0_RLC3_RB_RPTR ++#define SDMA0_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_RB_RPTR_HI ++#define SDMA0_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_RB_WPTR ++#define SDMA0_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_RB_WPTR_HI ++#define SDMA0_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_RB_WPTR_POLL_CNTL ++#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA0_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA0_RLC3_RB_RPTR_ADDR_HI ++#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_RB_RPTR_ADDR_LO ++#define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA0_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC3_IB_CNTL ++#define SDMA0_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA0_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA0_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA0_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA0_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA0_RLC3_IB_RPTR ++#define SDMA0_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC3_IB_OFFSET ++#define SDMA0_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC3_IB_BASE_LO ++#define SDMA0_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA0_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA0_RLC3_IB_BASE_HI ++#define SDMA0_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_IB_SIZE ++#define SDMA0_RLC3_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA0_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC3_SKIP_CNTL ++#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA0_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA0_RLC3_CONTEXT_STATUS ++#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA0_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA0_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA0_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA0_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA0_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA0_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA0_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA0_RLC3_DOORBELL ++#define SDMA0_RLC3_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA0_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA0_RLC3_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA0_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA0_RLC3_STATUS ++#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA0_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA0_RLC3_DOORBELL_LOG ++#define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA0_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA0_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA0_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA0_RLC3_WATERMARK ++#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA0_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA0_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA0_RLC3_DOORBELL_OFFSET ++#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA0_RLC3_CSA_ADDR_LO ++#define SDMA0_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC3_CSA_ADDR_HI ++#define SDMA0_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_IB_SUB_REMAIN ++#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA0_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC3_PREEMPT ++#define SDMA0_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA0_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA0_RLC3_DUMMY_REG ++#define SDMA0_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA0_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI ++#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO ++#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC3_RB_AQL_CNTL ++#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA0_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA0_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA0_RLC3_MINOR_PTR_UPDATE ++#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA0_RLC3_MIDCMD_DATA0 ++#define SDMA0_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA0_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_MIDCMD_DATA1 ++#define SDMA0_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA0_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_MIDCMD_DATA2 ++#define SDMA0_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA0_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_MIDCMD_DATA3 ++#define SDMA0_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA0_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_MIDCMD_DATA4 ++#define SDMA0_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA0_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_MIDCMD_DATA5 ++#define SDMA0_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA0_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_MIDCMD_DATA6 ++#define SDMA0_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA0_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_MIDCMD_DATA7 ++#define SDMA0_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA0_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_MIDCMD_DATA8 ++#define SDMA0_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA0_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA0_RLC3_MIDCMD_CNTL ++#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA0_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA0_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA0_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA0_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA0_RLC4_RB_CNTL ++#define SDMA0_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA0_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA0_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA0_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA0_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA0_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA0_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA0_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA0_RLC4_RB_BASE ++#define SDMA0_RLC4_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA0_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_RB_BASE_HI ++#define SDMA0_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA0_RLC4_RB_RPTR ++#define SDMA0_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_RB_RPTR_HI ++#define SDMA0_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_RB_WPTR ++#define SDMA0_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_RB_WPTR_HI ++#define SDMA0_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_RB_WPTR_POLL_CNTL ++#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA0_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA0_RLC4_RB_RPTR_ADDR_HI ++#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_RB_RPTR_ADDR_LO ++#define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA0_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC4_IB_CNTL ++#define SDMA0_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA0_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA0_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA0_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA0_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA0_RLC4_IB_RPTR ++#define SDMA0_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC4_IB_OFFSET ++#define SDMA0_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC4_IB_BASE_LO ++#define SDMA0_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA0_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA0_RLC4_IB_BASE_HI ++#define SDMA0_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_IB_SIZE ++#define SDMA0_RLC4_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA0_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC4_SKIP_CNTL ++#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA0_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA0_RLC4_CONTEXT_STATUS ++#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA0_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA0_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA0_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA0_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA0_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA0_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA0_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA0_RLC4_DOORBELL ++#define SDMA0_RLC4_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA0_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA0_RLC4_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA0_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA0_RLC4_STATUS ++#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA0_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA0_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA0_RLC4_DOORBELL_LOG ++#define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA0_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA0_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA0_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA0_RLC4_WATERMARK ++#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA0_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA0_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA0_RLC4_DOORBELL_OFFSET ++#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA0_RLC4_CSA_ADDR_LO ++#define SDMA0_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC4_CSA_ADDR_HI ++#define SDMA0_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_IB_SUB_REMAIN ++#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA0_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC4_PREEMPT ++#define SDMA0_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA0_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA0_RLC4_DUMMY_REG ++#define SDMA0_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA0_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI ++#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO ++#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC4_RB_AQL_CNTL ++#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA0_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA0_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA0_RLC4_MINOR_PTR_UPDATE ++#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA0_RLC4_MIDCMD_DATA0 ++#define SDMA0_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA0_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_MIDCMD_DATA1 ++#define SDMA0_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA0_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_MIDCMD_DATA2 ++#define SDMA0_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA0_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_MIDCMD_DATA3 ++#define SDMA0_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA0_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_MIDCMD_DATA4 ++#define SDMA0_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA0_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_MIDCMD_DATA5 ++#define SDMA0_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA0_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_MIDCMD_DATA6 ++#define SDMA0_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA0_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_MIDCMD_DATA7 ++#define SDMA0_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA0_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_MIDCMD_DATA8 ++#define SDMA0_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA0_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA0_RLC4_MIDCMD_CNTL ++#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA0_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA0_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA0_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA0_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA0_RLC5_RB_CNTL ++#define SDMA0_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA0_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA0_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA0_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA0_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA0_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA0_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA0_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA0_RLC5_RB_BASE ++#define SDMA0_RLC5_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA0_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_RB_BASE_HI ++#define SDMA0_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA0_RLC5_RB_RPTR ++#define SDMA0_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_RB_RPTR_HI ++#define SDMA0_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_RB_WPTR ++#define SDMA0_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_RB_WPTR_HI ++#define SDMA0_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_RB_WPTR_POLL_CNTL ++#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA0_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA0_RLC5_RB_RPTR_ADDR_HI ++#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_RB_RPTR_ADDR_LO ++#define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA0_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC5_IB_CNTL ++#define SDMA0_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA0_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA0_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA0_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA0_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA0_RLC5_IB_RPTR ++#define SDMA0_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC5_IB_OFFSET ++#define SDMA0_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC5_IB_BASE_LO ++#define SDMA0_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA0_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA0_RLC5_IB_BASE_HI ++#define SDMA0_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_IB_SIZE ++#define SDMA0_RLC5_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA0_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC5_SKIP_CNTL ++#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA0_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA0_RLC5_CONTEXT_STATUS ++#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA0_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA0_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA0_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA0_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA0_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA0_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA0_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA0_RLC5_DOORBELL ++#define SDMA0_RLC5_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA0_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA0_RLC5_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA0_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA0_RLC5_STATUS ++#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA0_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA0_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA0_RLC5_DOORBELL_LOG ++#define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA0_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA0_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA0_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA0_RLC5_WATERMARK ++#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA0_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA0_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA0_RLC5_DOORBELL_OFFSET ++#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA0_RLC5_CSA_ADDR_LO ++#define SDMA0_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC5_CSA_ADDR_HI ++#define SDMA0_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_IB_SUB_REMAIN ++#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA0_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC5_PREEMPT ++#define SDMA0_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA0_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA0_RLC5_DUMMY_REG ++#define SDMA0_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA0_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI ++#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO ++#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC5_RB_AQL_CNTL ++#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA0_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA0_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA0_RLC5_MINOR_PTR_UPDATE ++#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA0_RLC5_MIDCMD_DATA0 ++#define SDMA0_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA0_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_MIDCMD_DATA1 ++#define SDMA0_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA0_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_MIDCMD_DATA2 ++#define SDMA0_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA0_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_MIDCMD_DATA3 ++#define SDMA0_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA0_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_MIDCMD_DATA4 ++#define SDMA0_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA0_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_MIDCMD_DATA5 ++#define SDMA0_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA0_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_MIDCMD_DATA6 ++#define SDMA0_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA0_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_MIDCMD_DATA7 ++#define SDMA0_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA0_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_MIDCMD_DATA8 ++#define SDMA0_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA0_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA0_RLC5_MIDCMD_CNTL ++#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA0_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA0_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA0_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA0_RLC6_RB_CNTL ++#define SDMA0_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA0_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA0_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA0_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA0_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA0_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA0_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA0_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA0_RLC6_RB_BASE ++#define SDMA0_RLC6_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA0_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_RB_BASE_HI ++#define SDMA0_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA0_RLC6_RB_RPTR ++#define SDMA0_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_RB_RPTR_HI ++#define SDMA0_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_RB_WPTR ++#define SDMA0_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_RB_WPTR_HI ++#define SDMA0_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_RB_WPTR_POLL_CNTL ++#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA0_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA0_RLC6_RB_RPTR_ADDR_HI ++#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_RB_RPTR_ADDR_LO ++#define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA0_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC6_IB_CNTL ++#define SDMA0_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA0_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA0_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA0_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA0_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA0_RLC6_IB_RPTR ++#define SDMA0_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC6_IB_OFFSET ++#define SDMA0_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC6_IB_BASE_LO ++#define SDMA0_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA0_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA0_RLC6_IB_BASE_HI ++#define SDMA0_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_IB_SIZE ++#define SDMA0_RLC6_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA0_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC6_SKIP_CNTL ++#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA0_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA0_RLC6_CONTEXT_STATUS ++#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA0_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA0_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA0_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA0_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA0_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA0_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA0_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA0_RLC6_DOORBELL ++#define SDMA0_RLC6_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA0_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA0_RLC6_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA0_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA0_RLC6_STATUS ++#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA0_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA0_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA0_RLC6_DOORBELL_LOG ++#define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA0_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA0_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA0_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA0_RLC6_WATERMARK ++#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA0_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA0_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA0_RLC6_DOORBELL_OFFSET ++#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA0_RLC6_CSA_ADDR_LO ++#define SDMA0_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC6_CSA_ADDR_HI ++#define SDMA0_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_IB_SUB_REMAIN ++#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA0_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC6_PREEMPT ++#define SDMA0_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA0_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA0_RLC6_DUMMY_REG ++#define SDMA0_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA0_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI ++#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO ++#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC6_RB_AQL_CNTL ++#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA0_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA0_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA0_RLC6_MINOR_PTR_UPDATE ++#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA0_RLC6_MIDCMD_DATA0 ++#define SDMA0_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA0_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_MIDCMD_DATA1 ++#define SDMA0_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA0_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_MIDCMD_DATA2 ++#define SDMA0_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA0_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_MIDCMD_DATA3 ++#define SDMA0_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA0_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_MIDCMD_DATA4 ++#define SDMA0_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA0_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_MIDCMD_DATA5 ++#define SDMA0_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA0_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_MIDCMD_DATA6 ++#define SDMA0_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA0_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_MIDCMD_DATA7 ++#define SDMA0_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA0_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_MIDCMD_DATA8 ++#define SDMA0_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA0_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA0_RLC6_MIDCMD_CNTL ++#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA0_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA0_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA0_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA0_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA0_RLC7_RB_CNTL ++#define SDMA0_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA0_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA0_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA0_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA0_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA0_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA0_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA0_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA0_RLC7_RB_BASE ++#define SDMA0_RLC7_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA0_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_RB_BASE_HI ++#define SDMA0_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA0_RLC7_RB_RPTR ++#define SDMA0_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_RB_RPTR_HI ++#define SDMA0_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_RB_WPTR ++#define SDMA0_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_RB_WPTR_HI ++#define SDMA0_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA0_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_RB_WPTR_POLL_CNTL ++#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA0_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA0_RLC7_RB_RPTR_ADDR_HI ++#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_RB_RPTR_ADDR_LO ++#define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA0_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC7_IB_CNTL ++#define SDMA0_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA0_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA0_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA0_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA0_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA0_RLC7_IB_RPTR ++#define SDMA0_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC7_IB_OFFSET ++#define SDMA0_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA0_RLC7_IB_BASE_LO ++#define SDMA0_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA0_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA0_RLC7_IB_BASE_HI ++#define SDMA0_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_IB_SIZE ++#define SDMA0_RLC7_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA0_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC7_SKIP_CNTL ++#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA0_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA0_RLC7_CONTEXT_STATUS ++#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA0_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA0_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA0_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA0_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA0_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA0_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA0_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA0_RLC7_DOORBELL ++#define SDMA0_RLC7_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA0_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA0_RLC7_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA0_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA0_RLC7_STATUS ++#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA0_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA0_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA0_RLC7_DOORBELL_LOG ++#define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA0_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA0_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA0_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA0_RLC7_WATERMARK ++#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA0_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA0_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA0_RLC7_DOORBELL_OFFSET ++#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA0_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA0_RLC7_CSA_ADDR_LO ++#define SDMA0_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC7_CSA_ADDR_HI ++#define SDMA0_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_IB_SUB_REMAIN ++#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA0_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA0_RLC7_PREEMPT ++#define SDMA0_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA0_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA0_RLC7_DUMMY_REG ++#define SDMA0_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA0_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI ++#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO ++#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA0_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA0_RLC7_RB_AQL_CNTL ++#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA0_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA0_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA0_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA0_RLC7_MINOR_PTR_UPDATE ++#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA0_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA0_RLC7_MIDCMD_DATA0 ++#define SDMA0_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA0_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_MIDCMD_DATA1 ++#define SDMA0_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA0_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_MIDCMD_DATA2 ++#define SDMA0_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA0_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_MIDCMD_DATA3 ++#define SDMA0_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA0_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_MIDCMD_DATA4 ++#define SDMA0_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA0_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_MIDCMD_DATA5 ++#define SDMA0_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA0_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_MIDCMD_DATA6 ++#define SDMA0_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA0_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_MIDCMD_DATA7 ++#define SDMA0_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA0_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_MIDCMD_DATA8 ++#define SDMA0_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA0_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA0_RLC7_MIDCMD_CNTL ++#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA0_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA0_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA0_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h +new file mode 100644 +index 000000000000..db24d5eb16c9 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_offset.h +@@ -0,0 +1,1039 @@ ++/* ++ * Copyright (C) 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _sdma1_4_2_0_OFFSET_HEADER ++#define _sdma1_4_2_0_OFFSET_HEADER ++ ++ ++ ++// addressBlock: sdma1_sdma1dec ++// base address: 0x6180 ++#define mmSDMA1_UCODE_ADDR 0x0000 ++#define mmSDMA1_UCODE_ADDR_BASE_IDX 0 ++#define mmSDMA1_UCODE_DATA 0x0001 ++#define mmSDMA1_UCODE_DATA_BASE_IDX 0 ++#define mmSDMA1_VM_CNTL 0x0004 ++#define mmSDMA1_VM_CNTL_BASE_IDX 0 ++#define mmSDMA1_VM_CTX_LO 0x0005 ++#define mmSDMA1_VM_CTX_LO_BASE_IDX 0 ++#define mmSDMA1_VM_CTX_HI 0x0006 ++#define mmSDMA1_VM_CTX_HI_BASE_IDX 0 ++#define mmSDMA1_ACTIVE_FCN_ID 0x0007 ++#define mmSDMA1_ACTIVE_FCN_ID_BASE_IDX 0 ++#define mmSDMA1_VM_CTX_CNTL 0x0008 ++#define mmSDMA1_VM_CTX_CNTL_BASE_IDX 0 ++#define mmSDMA1_VIRT_RESET_REQ 0x0009 ++#define mmSDMA1_VIRT_RESET_REQ_BASE_IDX 0 ++#define mmSDMA1_VF_ENABLE 0x000a ++#define mmSDMA1_VF_ENABLE_BASE_IDX 0 ++#define mmSDMA1_CONTEXT_REG_TYPE0 0x000b ++#define mmSDMA1_CONTEXT_REG_TYPE0_BASE_IDX 0 ++#define mmSDMA1_CONTEXT_REG_TYPE1 0x000c ++#define mmSDMA1_CONTEXT_REG_TYPE1_BASE_IDX 0 ++#define mmSDMA1_CONTEXT_REG_TYPE2 0x000d ++#define mmSDMA1_CONTEXT_REG_TYPE2_BASE_IDX 0 ++#define mmSDMA1_CONTEXT_REG_TYPE3 0x000e ++#define mmSDMA1_CONTEXT_REG_TYPE3_BASE_IDX 0 ++#define mmSDMA1_PUB_REG_TYPE0 0x000f ++#define mmSDMA1_PUB_REG_TYPE0_BASE_IDX 0 ++#define mmSDMA1_PUB_REG_TYPE1 0x0010 ++#define mmSDMA1_PUB_REG_TYPE1_BASE_IDX 0 ++#define mmSDMA1_PUB_REG_TYPE2 0x0011 ++#define mmSDMA1_PUB_REG_TYPE2_BASE_IDX 0 ++#define mmSDMA1_PUB_REG_TYPE3 0x0012 ++#define mmSDMA1_PUB_REG_TYPE3_BASE_IDX 0 ++#define mmSDMA1_MMHUB_CNTL 0x0013 ++#define mmSDMA1_MMHUB_CNTL_BASE_IDX 0 ++#define mmSDMA1_CONTEXT_GROUP_BOUNDARY 0x0019 ++#define mmSDMA1_CONTEXT_GROUP_BOUNDARY_BASE_IDX 0 ++#define mmSDMA1_POWER_CNTL 0x001a ++#define mmSDMA1_POWER_CNTL_BASE_IDX 0 ++#define mmSDMA1_CLK_CTRL 0x001b ++#define mmSDMA1_CLK_CTRL_BASE_IDX 0 ++#define mmSDMA1_CNTL 0x001c ++#define mmSDMA1_CNTL_BASE_IDX 0 ++#define mmSDMA1_CHICKEN_BITS 0x001d ++#define mmSDMA1_CHICKEN_BITS_BASE_IDX 0 ++#define mmSDMA1_GB_ADDR_CONFIG 0x001e ++#define mmSDMA1_GB_ADDR_CONFIG_BASE_IDX 0 ++#define mmSDMA1_GB_ADDR_CONFIG_READ 0x001f ++#define mmSDMA1_GB_ADDR_CONFIG_READ_BASE_IDX 0 ++#define mmSDMA1_RB_RPTR_FETCH_HI 0x0020 ++#define mmSDMA1_RB_RPTR_FETCH_HI_BASE_IDX 0 ++#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 ++#define mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 0 ++#define mmSDMA1_RB_RPTR_FETCH 0x0022 ++#define mmSDMA1_RB_RPTR_FETCH_BASE_IDX 0 ++#define mmSDMA1_IB_OFFSET_FETCH 0x0023 ++#define mmSDMA1_IB_OFFSET_FETCH_BASE_IDX 0 ++#define mmSDMA1_PROGRAM 0x0024 ++#define mmSDMA1_PROGRAM_BASE_IDX 0 ++#define mmSDMA1_STATUS_REG 0x0025 ++#define mmSDMA1_STATUS_REG_BASE_IDX 0 ++#define mmSDMA1_STATUS1_REG 0x0026 ++#define mmSDMA1_STATUS1_REG_BASE_IDX 0 ++#define mmSDMA1_RD_BURST_CNTL 0x0027 ++#define mmSDMA1_RD_BURST_CNTL_BASE_IDX 0 ++#define mmSDMA1_HBM_PAGE_CONFIG 0x0028 ++#define mmSDMA1_HBM_PAGE_CONFIG_BASE_IDX 0 ++#define mmSDMA1_UCODE_CHECKSUM 0x0029 ++#define mmSDMA1_UCODE_CHECKSUM_BASE_IDX 0 ++#define mmSDMA1_F32_CNTL 0x002a ++#define mmSDMA1_F32_CNTL_BASE_IDX 0 ++#define mmSDMA1_FREEZE 0x002b ++#define mmSDMA1_FREEZE_BASE_IDX 0 ++#define mmSDMA1_PHASE0_QUANTUM 0x002c ++#define mmSDMA1_PHASE0_QUANTUM_BASE_IDX 0 ++#define mmSDMA1_PHASE1_QUANTUM 0x002d ++#define mmSDMA1_PHASE1_QUANTUM_BASE_IDX 0 ++#define mmSDMA1_EDC_CONFIG 0x0032 ++#define mmSDMA1_EDC_CONFIG_BASE_IDX 0 ++#define mmSDMA1_BA_THRESHOLD 0x0033 ++#define mmSDMA1_BA_THRESHOLD_BASE_IDX 0 ++#define mmSDMA1_ID 0x0034 ++#define mmSDMA1_ID_BASE_IDX 0 ++#define mmSDMA1_VERSION 0x0035 ++#define mmSDMA1_VERSION_BASE_IDX 0 ++#define mmSDMA1_EDC_COUNTER 0x0036 ++#define mmSDMA1_EDC_COUNTER_BASE_IDX 0 ++#define mmSDMA1_EDC_COUNTER_CLEAR 0x0037 ++#define mmSDMA1_EDC_COUNTER_CLEAR_BASE_IDX 0 ++#define mmSDMA1_STATUS2_REG 0x0038 ++#define mmSDMA1_STATUS2_REG_BASE_IDX 0 ++#define mmSDMA1_ATOMIC_CNTL 0x0039 ++#define mmSDMA1_ATOMIC_CNTL_BASE_IDX 0 ++#define mmSDMA1_ATOMIC_PREOP_LO 0x003a ++#define mmSDMA1_ATOMIC_PREOP_LO_BASE_IDX 0 ++#define mmSDMA1_ATOMIC_PREOP_HI 0x003b ++#define mmSDMA1_ATOMIC_PREOP_HI_BASE_IDX 0 ++#define mmSDMA1_UTCL1_CNTL 0x003c ++#define mmSDMA1_UTCL1_CNTL_BASE_IDX 0 ++#define mmSDMA1_UTCL1_WATERMK 0x003d ++#define mmSDMA1_UTCL1_WATERMK_BASE_IDX 0 ++#define mmSDMA1_UTCL1_RD_STATUS 0x003e ++#define mmSDMA1_UTCL1_RD_STATUS_BASE_IDX 0 ++#define mmSDMA1_UTCL1_WR_STATUS 0x003f ++#define mmSDMA1_UTCL1_WR_STATUS_BASE_IDX 0 ++#define mmSDMA1_UTCL1_INV0 0x0040 ++#define mmSDMA1_UTCL1_INV0_BASE_IDX 0 ++#define mmSDMA1_UTCL1_INV1 0x0041 ++#define mmSDMA1_UTCL1_INV1_BASE_IDX 0 ++#define mmSDMA1_UTCL1_INV2 0x0042 ++#define mmSDMA1_UTCL1_INV2_BASE_IDX 0 ++#define mmSDMA1_UTCL1_RD_XNACK0 0x0043 ++#define mmSDMA1_UTCL1_RD_XNACK0_BASE_IDX 0 ++#define mmSDMA1_UTCL1_RD_XNACK1 0x0044 ++#define mmSDMA1_UTCL1_RD_XNACK1_BASE_IDX 0 ++#define mmSDMA1_UTCL1_WR_XNACK0 0x0045 ++#define mmSDMA1_UTCL1_WR_XNACK0_BASE_IDX 0 ++#define mmSDMA1_UTCL1_WR_XNACK1 0x0046 ++#define mmSDMA1_UTCL1_WR_XNACK1_BASE_IDX 0 ++#define mmSDMA1_UTCL1_TIMEOUT 0x0047 ++#define mmSDMA1_UTCL1_TIMEOUT_BASE_IDX 0 ++#define mmSDMA1_UTCL1_PAGE 0x0048 ++#define mmSDMA1_UTCL1_PAGE_BASE_IDX 0 ++#define mmSDMA1_POWER_CNTL_IDLE 0x0049 ++#define mmSDMA1_POWER_CNTL_IDLE_BASE_IDX 0 ++#define mmSDMA1_RELAX_ORDERING_LUT 0x004a ++#define mmSDMA1_RELAX_ORDERING_LUT_BASE_IDX 0 ++#define mmSDMA1_CHICKEN_BITS_2 0x004b ++#define mmSDMA1_CHICKEN_BITS_2_BASE_IDX 0 ++#define mmSDMA1_STATUS3_REG 0x004c ++#define mmSDMA1_STATUS3_REG_BASE_IDX 0 ++#define mmSDMA1_PHYSICAL_ADDR_LO 0x004d ++#define mmSDMA1_PHYSICAL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_PHYSICAL_ADDR_HI 0x004e ++#define mmSDMA1_PHYSICAL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_PHASE2_QUANTUM 0x004f ++#define mmSDMA1_PHASE2_QUANTUM_BASE_IDX 0 ++#define mmSDMA1_ERROR_LOG 0x0050 ++#define mmSDMA1_ERROR_LOG_BASE_IDX 0 ++#define mmSDMA1_PUB_DUMMY_REG0 0x0051 ++#define mmSDMA1_PUB_DUMMY_REG0_BASE_IDX 0 ++#define mmSDMA1_PUB_DUMMY_REG1 0x0052 ++#define mmSDMA1_PUB_DUMMY_REG1_BASE_IDX 0 ++#define mmSDMA1_PUB_DUMMY_REG2 0x0053 ++#define mmSDMA1_PUB_DUMMY_REG2_BASE_IDX 0 ++#define mmSDMA1_PUB_DUMMY_REG3 0x0054 ++#define mmSDMA1_PUB_DUMMY_REG3_BASE_IDX 0 ++#define mmSDMA1_F32_COUNTER 0x0055 ++#define mmSDMA1_F32_COUNTER_BASE_IDX 0 ++#define mmSDMA1_PERFMON_CNTL 0x0057 ++#define mmSDMA1_PERFMON_CNTL_BASE_IDX 0 ++#define mmSDMA1_PERFCOUNTER0_RESULT 0x0058 ++#define mmSDMA1_PERFCOUNTER0_RESULT_BASE_IDX 0 ++#define mmSDMA1_PERFCOUNTER1_RESULT 0x0059 ++#define mmSDMA1_PERFCOUNTER1_RESULT_BASE_IDX 0 ++#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE 0x005a ++#define mmSDMA1_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 0 ++#define mmSDMA1_CRD_CNTL 0x005b ++#define mmSDMA1_CRD_CNTL_BASE_IDX 0 ++#define mmSDMA1_GPU_IOV_VIOLATION_LOG 0x005d ++#define mmSDMA1_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 ++#define mmSDMA1_ULV_CNTL 0x005e ++#define mmSDMA1_ULV_CNTL_BASE_IDX 0 ++#define mmSDMA1_EA_DBIT_ADDR_DATA 0x0060 ++#define mmSDMA1_EA_DBIT_ADDR_DATA_BASE_IDX 0 ++#define mmSDMA1_EA_DBIT_ADDR_INDEX 0x0061 ++#define mmSDMA1_EA_DBIT_ADDR_INDEX_BASE_IDX 0 ++#define mmSDMA1_GFX_RB_CNTL 0x0080 ++#define mmSDMA1_GFX_RB_CNTL_BASE_IDX 0 ++#define mmSDMA1_GFX_RB_BASE 0x0081 ++#define mmSDMA1_GFX_RB_BASE_BASE_IDX 0 ++#define mmSDMA1_GFX_RB_BASE_HI 0x0082 ++#define mmSDMA1_GFX_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_GFX_RB_RPTR 0x0083 ++#define mmSDMA1_GFX_RB_RPTR_BASE_IDX 0 ++#define mmSDMA1_GFX_RB_RPTR_HI 0x0084 ++#define mmSDMA1_GFX_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA1_GFX_RB_WPTR 0x0085 ++#define mmSDMA1_GFX_RB_WPTR_BASE_IDX 0 ++#define mmSDMA1_GFX_RB_WPTR_HI 0x0086 ++#define mmSDMA1_GFX_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL 0x0087 ++#define mmSDMA1_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA1_GFX_RB_RPTR_ADDR_HI 0x0088 ++#define mmSDMA1_GFX_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_GFX_RB_RPTR_ADDR_LO 0x0089 ++#define mmSDMA1_GFX_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_GFX_IB_CNTL 0x008a ++#define mmSDMA1_GFX_IB_CNTL_BASE_IDX 0 ++#define mmSDMA1_GFX_IB_RPTR 0x008b ++#define mmSDMA1_GFX_IB_RPTR_BASE_IDX 0 ++#define mmSDMA1_GFX_IB_OFFSET 0x008c ++#define mmSDMA1_GFX_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA1_GFX_IB_BASE_LO 0x008d ++#define mmSDMA1_GFX_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA1_GFX_IB_BASE_HI 0x008e ++#define mmSDMA1_GFX_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_GFX_IB_SIZE 0x008f ++#define mmSDMA1_GFX_IB_SIZE_BASE_IDX 0 ++#define mmSDMA1_GFX_SKIP_CNTL 0x0090 ++#define mmSDMA1_GFX_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA1_GFX_CONTEXT_STATUS 0x0091 ++#define mmSDMA1_GFX_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA1_GFX_DOORBELL 0x0092 ++#define mmSDMA1_GFX_DOORBELL_BASE_IDX 0 ++#define mmSDMA1_GFX_CONTEXT_CNTL 0x0093 ++#define mmSDMA1_GFX_CONTEXT_CNTL_BASE_IDX 0 ++#define mmSDMA1_GFX_STATUS 0x00a8 ++#define mmSDMA1_GFX_STATUS_BASE_IDX 0 ++#define mmSDMA1_GFX_DOORBELL_LOG 0x00a9 ++#define mmSDMA1_GFX_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA1_GFX_WATERMARK 0x00aa ++#define mmSDMA1_GFX_WATERMARK_BASE_IDX 0 ++#define mmSDMA1_GFX_DOORBELL_OFFSET 0x00ab ++#define mmSDMA1_GFX_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA1_GFX_CSA_ADDR_LO 0x00ac ++#define mmSDMA1_GFX_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_GFX_CSA_ADDR_HI 0x00ad ++#define mmSDMA1_GFX_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_GFX_IB_SUB_REMAIN 0x00af ++#define mmSDMA1_GFX_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA1_GFX_PREEMPT 0x00b0 ++#define mmSDMA1_GFX_PREEMPT_BASE_IDX 0 ++#define mmSDMA1_GFX_DUMMY_REG 0x00b1 ++#define mmSDMA1_GFX_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 ++#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 ++#define mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_GFX_RB_AQL_CNTL 0x00b4 ++#define mmSDMA1_GFX_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA1_GFX_MINOR_PTR_UPDATE 0x00b5 ++#define mmSDMA1_GFX_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA1_GFX_MIDCMD_DATA0 0x00c0 ++#define mmSDMA1_GFX_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA1_GFX_MIDCMD_DATA1 0x00c1 ++#define mmSDMA1_GFX_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA1_GFX_MIDCMD_DATA2 0x00c2 ++#define mmSDMA1_GFX_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA1_GFX_MIDCMD_DATA3 0x00c3 ++#define mmSDMA1_GFX_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA1_GFX_MIDCMD_DATA4 0x00c4 ++#define mmSDMA1_GFX_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA1_GFX_MIDCMD_DATA5 0x00c5 ++#define mmSDMA1_GFX_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA1_GFX_MIDCMD_DATA6 0x00c6 ++#define mmSDMA1_GFX_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA1_GFX_MIDCMD_DATA7 0x00c7 ++#define mmSDMA1_GFX_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA1_GFX_MIDCMD_DATA8 0x00c8 ++#define mmSDMA1_GFX_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA1_GFX_MIDCMD_CNTL 0x00c9 ++#define mmSDMA1_GFX_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA1_PAGE_RB_CNTL 0x00e0 ++#define mmSDMA1_PAGE_RB_CNTL_BASE_IDX 0 ++#define mmSDMA1_PAGE_RB_BASE 0x00e1 ++#define mmSDMA1_PAGE_RB_BASE_BASE_IDX 0 ++#define mmSDMA1_PAGE_RB_BASE_HI 0x00e2 ++#define mmSDMA1_PAGE_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_PAGE_RB_RPTR 0x00e3 ++#define mmSDMA1_PAGE_RB_RPTR_BASE_IDX 0 ++#define mmSDMA1_PAGE_RB_RPTR_HI 0x00e4 ++#define mmSDMA1_PAGE_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA1_PAGE_RB_WPTR 0x00e5 ++#define mmSDMA1_PAGE_RB_WPTR_BASE_IDX 0 ++#define mmSDMA1_PAGE_RB_WPTR_HI 0x00e6 ++#define mmSDMA1_PAGE_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL 0x00e7 ++#define mmSDMA1_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI 0x00e8 ++#define mmSDMA1_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO 0x00e9 ++#define mmSDMA1_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_PAGE_IB_CNTL 0x00ea ++#define mmSDMA1_PAGE_IB_CNTL_BASE_IDX 0 ++#define mmSDMA1_PAGE_IB_RPTR 0x00eb ++#define mmSDMA1_PAGE_IB_RPTR_BASE_IDX 0 ++#define mmSDMA1_PAGE_IB_OFFSET 0x00ec ++#define mmSDMA1_PAGE_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA1_PAGE_IB_BASE_LO 0x00ed ++#define mmSDMA1_PAGE_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA1_PAGE_IB_BASE_HI 0x00ee ++#define mmSDMA1_PAGE_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_PAGE_IB_SIZE 0x00ef ++#define mmSDMA1_PAGE_IB_SIZE_BASE_IDX 0 ++#define mmSDMA1_PAGE_SKIP_CNTL 0x00f0 ++#define mmSDMA1_PAGE_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA1_PAGE_CONTEXT_STATUS 0x00f1 ++#define mmSDMA1_PAGE_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA1_PAGE_DOORBELL 0x00f2 ++#define mmSDMA1_PAGE_DOORBELL_BASE_IDX 0 ++#define mmSDMA1_PAGE_STATUS 0x0108 ++#define mmSDMA1_PAGE_STATUS_BASE_IDX 0 ++#define mmSDMA1_PAGE_DOORBELL_LOG 0x0109 ++#define mmSDMA1_PAGE_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA1_PAGE_WATERMARK 0x010a ++#define mmSDMA1_PAGE_WATERMARK_BASE_IDX 0 ++#define mmSDMA1_PAGE_DOORBELL_OFFSET 0x010b ++#define mmSDMA1_PAGE_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA1_PAGE_CSA_ADDR_LO 0x010c ++#define mmSDMA1_PAGE_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_PAGE_CSA_ADDR_HI 0x010d ++#define mmSDMA1_PAGE_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_PAGE_IB_SUB_REMAIN 0x010f ++#define mmSDMA1_PAGE_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA1_PAGE_PREEMPT 0x0110 ++#define mmSDMA1_PAGE_PREEMPT_BASE_IDX 0 ++#define mmSDMA1_PAGE_DUMMY_REG 0x0111 ++#define mmSDMA1_PAGE_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI 0x0112 ++#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO 0x0113 ++#define mmSDMA1_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_PAGE_RB_AQL_CNTL 0x0114 ++#define mmSDMA1_PAGE_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA1_PAGE_MINOR_PTR_UPDATE 0x0115 ++#define mmSDMA1_PAGE_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA1_PAGE_MIDCMD_DATA0 0x0120 ++#define mmSDMA1_PAGE_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA1_PAGE_MIDCMD_DATA1 0x0121 ++#define mmSDMA1_PAGE_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA1_PAGE_MIDCMD_DATA2 0x0122 ++#define mmSDMA1_PAGE_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA1_PAGE_MIDCMD_DATA3 0x0123 ++#define mmSDMA1_PAGE_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA1_PAGE_MIDCMD_DATA4 0x0124 ++#define mmSDMA1_PAGE_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA1_PAGE_MIDCMD_DATA5 0x0125 ++#define mmSDMA1_PAGE_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA1_PAGE_MIDCMD_DATA6 0x0126 ++#define mmSDMA1_PAGE_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA1_PAGE_MIDCMD_DATA7 0x0127 ++#define mmSDMA1_PAGE_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA1_PAGE_MIDCMD_DATA8 0x0128 ++#define mmSDMA1_PAGE_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA1_PAGE_MIDCMD_CNTL 0x0129 ++#define mmSDMA1_PAGE_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC0_RB_CNTL 0x0140 ++#define mmSDMA1_RLC0_RB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC0_RB_BASE 0x0141 ++#define mmSDMA1_RLC0_RB_BASE_BASE_IDX 0 ++#define mmSDMA1_RLC0_RB_BASE_HI 0x0142 ++#define mmSDMA1_RLC0_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC0_RB_RPTR 0x0143 ++#define mmSDMA1_RLC0_RB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC0_RB_RPTR_HI 0x0144 ++#define mmSDMA1_RLC0_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC0_RB_WPTR 0x0145 ++#define mmSDMA1_RLC0_RB_WPTR_BASE_IDX 0 ++#define mmSDMA1_RLC0_RB_WPTR_HI 0x0146 ++#define mmSDMA1_RLC0_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL 0x0147 ++#define mmSDMA1_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI 0x0148 ++#define mmSDMA1_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO 0x0149 ++#define mmSDMA1_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC0_IB_CNTL 0x014a ++#define mmSDMA1_RLC0_IB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC0_IB_RPTR 0x014b ++#define mmSDMA1_RLC0_IB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC0_IB_OFFSET 0x014c ++#define mmSDMA1_RLC0_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC0_IB_BASE_LO 0x014d ++#define mmSDMA1_RLC0_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA1_RLC0_IB_BASE_HI 0x014e ++#define mmSDMA1_RLC0_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC0_IB_SIZE 0x014f ++#define mmSDMA1_RLC0_IB_SIZE_BASE_IDX 0 ++#define mmSDMA1_RLC0_SKIP_CNTL 0x0150 ++#define mmSDMA1_RLC0_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC0_CONTEXT_STATUS 0x0151 ++#define mmSDMA1_RLC0_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC0_DOORBELL 0x0152 ++#define mmSDMA1_RLC0_DOORBELL_BASE_IDX 0 ++#define mmSDMA1_RLC0_STATUS 0x0168 ++#define mmSDMA1_RLC0_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC0_DOORBELL_LOG 0x0169 ++#define mmSDMA1_RLC0_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA1_RLC0_WATERMARK 0x016a ++#define mmSDMA1_RLC0_WATERMARK_BASE_IDX 0 ++#define mmSDMA1_RLC0_DOORBELL_OFFSET 0x016b ++#define mmSDMA1_RLC0_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC0_CSA_ADDR_LO 0x016c ++#define mmSDMA1_RLC0_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC0_CSA_ADDR_HI 0x016d ++#define mmSDMA1_RLC0_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC0_IB_SUB_REMAIN 0x016f ++#define mmSDMA1_RLC0_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA1_RLC0_PREEMPT 0x0170 ++#define mmSDMA1_RLC0_PREEMPT_BASE_IDX 0 ++#define mmSDMA1_RLC0_DUMMY_REG 0x0171 ++#define mmSDMA1_RLC0_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI 0x0172 ++#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO 0x0173 ++#define mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC0_RB_AQL_CNTL 0x0174 ++#define mmSDMA1_RLC0_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC0_MINOR_PTR_UPDATE 0x0175 ++#define mmSDMA1_RLC0_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA1_RLC0_MIDCMD_DATA0 0x0180 ++#define mmSDMA1_RLC0_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA1_RLC0_MIDCMD_DATA1 0x0181 ++#define mmSDMA1_RLC0_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA1_RLC0_MIDCMD_DATA2 0x0182 ++#define mmSDMA1_RLC0_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA1_RLC0_MIDCMD_DATA3 0x0183 ++#define mmSDMA1_RLC0_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA1_RLC0_MIDCMD_DATA4 0x0184 ++#define mmSDMA1_RLC0_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA1_RLC0_MIDCMD_DATA5 0x0185 ++#define mmSDMA1_RLC0_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA1_RLC0_MIDCMD_DATA6 0x0186 ++#define mmSDMA1_RLC0_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA1_RLC0_MIDCMD_DATA7 0x0187 ++#define mmSDMA1_RLC0_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA1_RLC0_MIDCMD_DATA8 0x0188 ++#define mmSDMA1_RLC0_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA1_RLC0_MIDCMD_CNTL 0x0189 ++#define mmSDMA1_RLC0_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC1_RB_CNTL 0x01a0 ++#define mmSDMA1_RLC1_RB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC1_RB_BASE 0x01a1 ++#define mmSDMA1_RLC1_RB_BASE_BASE_IDX 0 ++#define mmSDMA1_RLC1_RB_BASE_HI 0x01a2 ++#define mmSDMA1_RLC1_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC1_RB_RPTR 0x01a3 ++#define mmSDMA1_RLC1_RB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC1_RB_RPTR_HI 0x01a4 ++#define mmSDMA1_RLC1_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC1_RB_WPTR 0x01a5 ++#define mmSDMA1_RLC1_RB_WPTR_BASE_IDX 0 ++#define mmSDMA1_RLC1_RB_WPTR_HI 0x01a6 ++#define mmSDMA1_RLC1_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL 0x01a7 ++#define mmSDMA1_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI 0x01a8 ++#define mmSDMA1_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO 0x01a9 ++#define mmSDMA1_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC1_IB_CNTL 0x01aa ++#define mmSDMA1_RLC1_IB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC1_IB_RPTR 0x01ab ++#define mmSDMA1_RLC1_IB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC1_IB_OFFSET 0x01ac ++#define mmSDMA1_RLC1_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC1_IB_BASE_LO 0x01ad ++#define mmSDMA1_RLC1_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA1_RLC1_IB_BASE_HI 0x01ae ++#define mmSDMA1_RLC1_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC1_IB_SIZE 0x01af ++#define mmSDMA1_RLC1_IB_SIZE_BASE_IDX 0 ++#define mmSDMA1_RLC1_SKIP_CNTL 0x01b0 ++#define mmSDMA1_RLC1_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC1_CONTEXT_STATUS 0x01b1 ++#define mmSDMA1_RLC1_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC1_DOORBELL 0x01b2 ++#define mmSDMA1_RLC1_DOORBELL_BASE_IDX 0 ++#define mmSDMA1_RLC1_STATUS 0x01c8 ++#define mmSDMA1_RLC1_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC1_DOORBELL_LOG 0x01c9 ++#define mmSDMA1_RLC1_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA1_RLC1_WATERMARK 0x01ca ++#define mmSDMA1_RLC1_WATERMARK_BASE_IDX 0 ++#define mmSDMA1_RLC1_DOORBELL_OFFSET 0x01cb ++#define mmSDMA1_RLC1_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC1_CSA_ADDR_LO 0x01cc ++#define mmSDMA1_RLC1_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC1_CSA_ADDR_HI 0x01cd ++#define mmSDMA1_RLC1_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC1_IB_SUB_REMAIN 0x01cf ++#define mmSDMA1_RLC1_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA1_RLC1_PREEMPT 0x01d0 ++#define mmSDMA1_RLC1_PREEMPT_BASE_IDX 0 ++#define mmSDMA1_RLC1_DUMMY_REG 0x01d1 ++#define mmSDMA1_RLC1_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI 0x01d2 ++#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO 0x01d3 ++#define mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC1_RB_AQL_CNTL 0x01d4 ++#define mmSDMA1_RLC1_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC1_MINOR_PTR_UPDATE 0x01d5 ++#define mmSDMA1_RLC1_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA1_RLC1_MIDCMD_DATA0 0x01e0 ++#define mmSDMA1_RLC1_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA1_RLC1_MIDCMD_DATA1 0x01e1 ++#define mmSDMA1_RLC1_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA1_RLC1_MIDCMD_DATA2 0x01e2 ++#define mmSDMA1_RLC1_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA1_RLC1_MIDCMD_DATA3 0x01e3 ++#define mmSDMA1_RLC1_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA1_RLC1_MIDCMD_DATA4 0x01e4 ++#define mmSDMA1_RLC1_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA1_RLC1_MIDCMD_DATA5 0x01e5 ++#define mmSDMA1_RLC1_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA1_RLC1_MIDCMD_DATA6 0x01e6 ++#define mmSDMA1_RLC1_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA1_RLC1_MIDCMD_DATA7 0x01e7 ++#define mmSDMA1_RLC1_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA1_RLC1_MIDCMD_DATA8 0x01e8 ++#define mmSDMA1_RLC1_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA1_RLC1_MIDCMD_CNTL 0x01e9 ++#define mmSDMA1_RLC1_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC2_RB_CNTL 0x0200 ++#define mmSDMA1_RLC2_RB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC2_RB_BASE 0x0201 ++#define mmSDMA1_RLC2_RB_BASE_BASE_IDX 0 ++#define mmSDMA1_RLC2_RB_BASE_HI 0x0202 ++#define mmSDMA1_RLC2_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC2_RB_RPTR 0x0203 ++#define mmSDMA1_RLC2_RB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC2_RB_RPTR_HI 0x0204 ++#define mmSDMA1_RLC2_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC2_RB_WPTR 0x0205 ++#define mmSDMA1_RLC2_RB_WPTR_BASE_IDX 0 ++#define mmSDMA1_RLC2_RB_WPTR_HI 0x0206 ++#define mmSDMA1_RLC2_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL 0x0207 ++#define mmSDMA1_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC2_RB_RPTR_ADDR_HI 0x0208 ++#define mmSDMA1_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC2_RB_RPTR_ADDR_LO 0x0209 ++#define mmSDMA1_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC2_IB_CNTL 0x020a ++#define mmSDMA1_RLC2_IB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC2_IB_RPTR 0x020b ++#define mmSDMA1_RLC2_IB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC2_IB_OFFSET 0x020c ++#define mmSDMA1_RLC2_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC2_IB_BASE_LO 0x020d ++#define mmSDMA1_RLC2_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA1_RLC2_IB_BASE_HI 0x020e ++#define mmSDMA1_RLC2_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC2_IB_SIZE 0x020f ++#define mmSDMA1_RLC2_IB_SIZE_BASE_IDX 0 ++#define mmSDMA1_RLC2_SKIP_CNTL 0x0210 ++#define mmSDMA1_RLC2_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC2_CONTEXT_STATUS 0x0211 ++#define mmSDMA1_RLC2_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC2_DOORBELL 0x0212 ++#define mmSDMA1_RLC2_DOORBELL_BASE_IDX 0 ++#define mmSDMA1_RLC2_STATUS 0x0228 ++#define mmSDMA1_RLC2_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC2_DOORBELL_LOG 0x0229 ++#define mmSDMA1_RLC2_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA1_RLC2_WATERMARK 0x022a ++#define mmSDMA1_RLC2_WATERMARK_BASE_IDX 0 ++#define mmSDMA1_RLC2_DOORBELL_OFFSET 0x022b ++#define mmSDMA1_RLC2_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC2_CSA_ADDR_LO 0x022c ++#define mmSDMA1_RLC2_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC2_CSA_ADDR_HI 0x022d ++#define mmSDMA1_RLC2_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC2_IB_SUB_REMAIN 0x022f ++#define mmSDMA1_RLC2_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA1_RLC2_PREEMPT 0x0230 ++#define mmSDMA1_RLC2_PREEMPT_BASE_IDX 0 ++#define mmSDMA1_RLC2_DUMMY_REG 0x0231 ++#define mmSDMA1_RLC2_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI 0x0232 ++#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO 0x0233 ++#define mmSDMA1_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC2_RB_AQL_CNTL 0x0234 ++#define mmSDMA1_RLC2_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC2_MINOR_PTR_UPDATE 0x0235 ++#define mmSDMA1_RLC2_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA1_RLC2_MIDCMD_DATA0 0x0240 ++#define mmSDMA1_RLC2_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA1_RLC2_MIDCMD_DATA1 0x0241 ++#define mmSDMA1_RLC2_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA1_RLC2_MIDCMD_DATA2 0x0242 ++#define mmSDMA1_RLC2_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA1_RLC2_MIDCMD_DATA3 0x0243 ++#define mmSDMA1_RLC2_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA1_RLC2_MIDCMD_DATA4 0x0244 ++#define mmSDMA1_RLC2_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA1_RLC2_MIDCMD_DATA5 0x0245 ++#define mmSDMA1_RLC2_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA1_RLC2_MIDCMD_DATA6 0x0246 ++#define mmSDMA1_RLC2_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA1_RLC2_MIDCMD_DATA7 0x0247 ++#define mmSDMA1_RLC2_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA1_RLC2_MIDCMD_DATA8 0x0248 ++#define mmSDMA1_RLC2_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA1_RLC2_MIDCMD_CNTL 0x0249 ++#define mmSDMA1_RLC2_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC3_RB_CNTL 0x0260 ++#define mmSDMA1_RLC3_RB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC3_RB_BASE 0x0261 ++#define mmSDMA1_RLC3_RB_BASE_BASE_IDX 0 ++#define mmSDMA1_RLC3_RB_BASE_HI 0x0262 ++#define mmSDMA1_RLC3_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC3_RB_RPTR 0x0263 ++#define mmSDMA1_RLC3_RB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC3_RB_RPTR_HI 0x0264 ++#define mmSDMA1_RLC3_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC3_RB_WPTR 0x0265 ++#define mmSDMA1_RLC3_RB_WPTR_BASE_IDX 0 ++#define mmSDMA1_RLC3_RB_WPTR_HI 0x0266 ++#define mmSDMA1_RLC3_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL 0x0267 ++#define mmSDMA1_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC3_RB_RPTR_ADDR_HI 0x0268 ++#define mmSDMA1_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC3_RB_RPTR_ADDR_LO 0x0269 ++#define mmSDMA1_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC3_IB_CNTL 0x026a ++#define mmSDMA1_RLC3_IB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC3_IB_RPTR 0x026b ++#define mmSDMA1_RLC3_IB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC3_IB_OFFSET 0x026c ++#define mmSDMA1_RLC3_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC3_IB_BASE_LO 0x026d ++#define mmSDMA1_RLC3_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA1_RLC3_IB_BASE_HI 0x026e ++#define mmSDMA1_RLC3_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC3_IB_SIZE 0x026f ++#define mmSDMA1_RLC3_IB_SIZE_BASE_IDX 0 ++#define mmSDMA1_RLC3_SKIP_CNTL 0x0270 ++#define mmSDMA1_RLC3_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC3_CONTEXT_STATUS 0x0271 ++#define mmSDMA1_RLC3_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC3_DOORBELL 0x0272 ++#define mmSDMA1_RLC3_DOORBELL_BASE_IDX 0 ++#define mmSDMA1_RLC3_STATUS 0x0288 ++#define mmSDMA1_RLC3_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC3_DOORBELL_LOG 0x0289 ++#define mmSDMA1_RLC3_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA1_RLC3_WATERMARK 0x028a ++#define mmSDMA1_RLC3_WATERMARK_BASE_IDX 0 ++#define mmSDMA1_RLC3_DOORBELL_OFFSET 0x028b ++#define mmSDMA1_RLC3_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC3_CSA_ADDR_LO 0x028c ++#define mmSDMA1_RLC3_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC3_CSA_ADDR_HI 0x028d ++#define mmSDMA1_RLC3_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC3_IB_SUB_REMAIN 0x028f ++#define mmSDMA1_RLC3_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA1_RLC3_PREEMPT 0x0290 ++#define mmSDMA1_RLC3_PREEMPT_BASE_IDX 0 ++#define mmSDMA1_RLC3_DUMMY_REG 0x0291 ++#define mmSDMA1_RLC3_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI 0x0292 ++#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO 0x0293 ++#define mmSDMA1_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC3_RB_AQL_CNTL 0x0294 ++#define mmSDMA1_RLC3_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC3_MINOR_PTR_UPDATE 0x0295 ++#define mmSDMA1_RLC3_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA1_RLC3_MIDCMD_DATA0 0x02a0 ++#define mmSDMA1_RLC3_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA1_RLC3_MIDCMD_DATA1 0x02a1 ++#define mmSDMA1_RLC3_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA1_RLC3_MIDCMD_DATA2 0x02a2 ++#define mmSDMA1_RLC3_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA1_RLC3_MIDCMD_DATA3 0x02a3 ++#define mmSDMA1_RLC3_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA1_RLC3_MIDCMD_DATA4 0x02a4 ++#define mmSDMA1_RLC3_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA1_RLC3_MIDCMD_DATA5 0x02a5 ++#define mmSDMA1_RLC3_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA1_RLC3_MIDCMD_DATA6 0x02a6 ++#define mmSDMA1_RLC3_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA1_RLC3_MIDCMD_DATA7 0x02a7 ++#define mmSDMA1_RLC3_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA1_RLC3_MIDCMD_DATA8 0x02a8 ++#define mmSDMA1_RLC3_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA1_RLC3_MIDCMD_CNTL 0x02a9 ++#define mmSDMA1_RLC3_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC4_RB_CNTL 0x02c0 ++#define mmSDMA1_RLC4_RB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC4_RB_BASE 0x02c1 ++#define mmSDMA1_RLC4_RB_BASE_BASE_IDX 0 ++#define mmSDMA1_RLC4_RB_BASE_HI 0x02c2 ++#define mmSDMA1_RLC4_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC4_RB_RPTR 0x02c3 ++#define mmSDMA1_RLC4_RB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC4_RB_RPTR_HI 0x02c4 ++#define mmSDMA1_RLC4_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC4_RB_WPTR 0x02c5 ++#define mmSDMA1_RLC4_RB_WPTR_BASE_IDX 0 ++#define mmSDMA1_RLC4_RB_WPTR_HI 0x02c6 ++#define mmSDMA1_RLC4_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL 0x02c7 ++#define mmSDMA1_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC4_RB_RPTR_ADDR_HI 0x02c8 ++#define mmSDMA1_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC4_RB_RPTR_ADDR_LO 0x02c9 ++#define mmSDMA1_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC4_IB_CNTL 0x02ca ++#define mmSDMA1_RLC4_IB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC4_IB_RPTR 0x02cb ++#define mmSDMA1_RLC4_IB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC4_IB_OFFSET 0x02cc ++#define mmSDMA1_RLC4_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC4_IB_BASE_LO 0x02cd ++#define mmSDMA1_RLC4_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA1_RLC4_IB_BASE_HI 0x02ce ++#define mmSDMA1_RLC4_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC4_IB_SIZE 0x02cf ++#define mmSDMA1_RLC4_IB_SIZE_BASE_IDX 0 ++#define mmSDMA1_RLC4_SKIP_CNTL 0x02d0 ++#define mmSDMA1_RLC4_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC4_CONTEXT_STATUS 0x02d1 ++#define mmSDMA1_RLC4_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC4_DOORBELL 0x02d2 ++#define mmSDMA1_RLC4_DOORBELL_BASE_IDX 0 ++#define mmSDMA1_RLC4_STATUS 0x02e8 ++#define mmSDMA1_RLC4_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC4_DOORBELL_LOG 0x02e9 ++#define mmSDMA1_RLC4_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA1_RLC4_WATERMARK 0x02ea ++#define mmSDMA1_RLC4_WATERMARK_BASE_IDX 0 ++#define mmSDMA1_RLC4_DOORBELL_OFFSET 0x02eb ++#define mmSDMA1_RLC4_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC4_CSA_ADDR_LO 0x02ec ++#define mmSDMA1_RLC4_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC4_CSA_ADDR_HI 0x02ed ++#define mmSDMA1_RLC4_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC4_IB_SUB_REMAIN 0x02ef ++#define mmSDMA1_RLC4_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA1_RLC4_PREEMPT 0x02f0 ++#define mmSDMA1_RLC4_PREEMPT_BASE_IDX 0 ++#define mmSDMA1_RLC4_DUMMY_REG 0x02f1 ++#define mmSDMA1_RLC4_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI 0x02f2 ++#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO 0x02f3 ++#define mmSDMA1_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC4_RB_AQL_CNTL 0x02f4 ++#define mmSDMA1_RLC4_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC4_MINOR_PTR_UPDATE 0x02f5 ++#define mmSDMA1_RLC4_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA1_RLC4_MIDCMD_DATA0 0x0300 ++#define mmSDMA1_RLC4_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA1_RLC4_MIDCMD_DATA1 0x0301 ++#define mmSDMA1_RLC4_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA1_RLC4_MIDCMD_DATA2 0x0302 ++#define mmSDMA1_RLC4_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA1_RLC4_MIDCMD_DATA3 0x0303 ++#define mmSDMA1_RLC4_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA1_RLC4_MIDCMD_DATA4 0x0304 ++#define mmSDMA1_RLC4_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA1_RLC4_MIDCMD_DATA5 0x0305 ++#define mmSDMA1_RLC4_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA1_RLC4_MIDCMD_DATA6 0x0306 ++#define mmSDMA1_RLC4_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA1_RLC4_MIDCMD_DATA7 0x0307 ++#define mmSDMA1_RLC4_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA1_RLC4_MIDCMD_DATA8 0x0308 ++#define mmSDMA1_RLC4_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA1_RLC4_MIDCMD_CNTL 0x0309 ++#define mmSDMA1_RLC4_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC5_RB_CNTL 0x0320 ++#define mmSDMA1_RLC5_RB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC5_RB_BASE 0x0321 ++#define mmSDMA1_RLC5_RB_BASE_BASE_IDX 0 ++#define mmSDMA1_RLC5_RB_BASE_HI 0x0322 ++#define mmSDMA1_RLC5_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC5_RB_RPTR 0x0323 ++#define mmSDMA1_RLC5_RB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC5_RB_RPTR_HI 0x0324 ++#define mmSDMA1_RLC5_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC5_RB_WPTR 0x0325 ++#define mmSDMA1_RLC5_RB_WPTR_BASE_IDX 0 ++#define mmSDMA1_RLC5_RB_WPTR_HI 0x0326 ++#define mmSDMA1_RLC5_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL 0x0327 ++#define mmSDMA1_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC5_RB_RPTR_ADDR_HI 0x0328 ++#define mmSDMA1_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC5_RB_RPTR_ADDR_LO 0x0329 ++#define mmSDMA1_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC5_IB_CNTL 0x032a ++#define mmSDMA1_RLC5_IB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC5_IB_RPTR 0x032b ++#define mmSDMA1_RLC5_IB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC5_IB_OFFSET 0x032c ++#define mmSDMA1_RLC5_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC5_IB_BASE_LO 0x032d ++#define mmSDMA1_RLC5_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA1_RLC5_IB_BASE_HI 0x032e ++#define mmSDMA1_RLC5_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC5_IB_SIZE 0x032f ++#define mmSDMA1_RLC5_IB_SIZE_BASE_IDX 0 ++#define mmSDMA1_RLC5_SKIP_CNTL 0x0330 ++#define mmSDMA1_RLC5_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC5_CONTEXT_STATUS 0x0331 ++#define mmSDMA1_RLC5_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC5_DOORBELL 0x0332 ++#define mmSDMA1_RLC5_DOORBELL_BASE_IDX 0 ++#define mmSDMA1_RLC5_STATUS 0x0348 ++#define mmSDMA1_RLC5_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC5_DOORBELL_LOG 0x0349 ++#define mmSDMA1_RLC5_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA1_RLC5_WATERMARK 0x034a ++#define mmSDMA1_RLC5_WATERMARK_BASE_IDX 0 ++#define mmSDMA1_RLC5_DOORBELL_OFFSET 0x034b ++#define mmSDMA1_RLC5_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC5_CSA_ADDR_LO 0x034c ++#define mmSDMA1_RLC5_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC5_CSA_ADDR_HI 0x034d ++#define mmSDMA1_RLC5_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC5_IB_SUB_REMAIN 0x034f ++#define mmSDMA1_RLC5_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA1_RLC5_PREEMPT 0x0350 ++#define mmSDMA1_RLC5_PREEMPT_BASE_IDX 0 ++#define mmSDMA1_RLC5_DUMMY_REG 0x0351 ++#define mmSDMA1_RLC5_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI 0x0352 ++#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO 0x0353 ++#define mmSDMA1_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC5_RB_AQL_CNTL 0x0354 ++#define mmSDMA1_RLC5_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC5_MINOR_PTR_UPDATE 0x0355 ++#define mmSDMA1_RLC5_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA1_RLC5_MIDCMD_DATA0 0x0360 ++#define mmSDMA1_RLC5_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA1_RLC5_MIDCMD_DATA1 0x0361 ++#define mmSDMA1_RLC5_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA1_RLC5_MIDCMD_DATA2 0x0362 ++#define mmSDMA1_RLC5_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA1_RLC5_MIDCMD_DATA3 0x0363 ++#define mmSDMA1_RLC5_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA1_RLC5_MIDCMD_DATA4 0x0364 ++#define mmSDMA1_RLC5_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA1_RLC5_MIDCMD_DATA5 0x0365 ++#define mmSDMA1_RLC5_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA1_RLC5_MIDCMD_DATA6 0x0366 ++#define mmSDMA1_RLC5_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA1_RLC5_MIDCMD_DATA7 0x0367 ++#define mmSDMA1_RLC5_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA1_RLC5_MIDCMD_DATA8 0x0368 ++#define mmSDMA1_RLC5_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA1_RLC5_MIDCMD_CNTL 0x0369 ++#define mmSDMA1_RLC5_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC6_RB_CNTL 0x0380 ++#define mmSDMA1_RLC6_RB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC6_RB_BASE 0x0381 ++#define mmSDMA1_RLC6_RB_BASE_BASE_IDX 0 ++#define mmSDMA1_RLC6_RB_BASE_HI 0x0382 ++#define mmSDMA1_RLC6_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC6_RB_RPTR 0x0383 ++#define mmSDMA1_RLC6_RB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC6_RB_RPTR_HI 0x0384 ++#define mmSDMA1_RLC6_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC6_RB_WPTR 0x0385 ++#define mmSDMA1_RLC6_RB_WPTR_BASE_IDX 0 ++#define mmSDMA1_RLC6_RB_WPTR_HI 0x0386 ++#define mmSDMA1_RLC6_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL 0x0387 ++#define mmSDMA1_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC6_RB_RPTR_ADDR_HI 0x0388 ++#define mmSDMA1_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC6_RB_RPTR_ADDR_LO 0x0389 ++#define mmSDMA1_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC6_IB_CNTL 0x038a ++#define mmSDMA1_RLC6_IB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC6_IB_RPTR 0x038b ++#define mmSDMA1_RLC6_IB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC6_IB_OFFSET 0x038c ++#define mmSDMA1_RLC6_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC6_IB_BASE_LO 0x038d ++#define mmSDMA1_RLC6_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA1_RLC6_IB_BASE_HI 0x038e ++#define mmSDMA1_RLC6_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC6_IB_SIZE 0x038f ++#define mmSDMA1_RLC6_IB_SIZE_BASE_IDX 0 ++#define mmSDMA1_RLC6_SKIP_CNTL 0x0390 ++#define mmSDMA1_RLC6_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC6_CONTEXT_STATUS 0x0391 ++#define mmSDMA1_RLC6_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC6_DOORBELL 0x0392 ++#define mmSDMA1_RLC6_DOORBELL_BASE_IDX 0 ++#define mmSDMA1_RLC6_STATUS 0x03a8 ++#define mmSDMA1_RLC6_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC6_DOORBELL_LOG 0x03a9 ++#define mmSDMA1_RLC6_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA1_RLC6_WATERMARK 0x03aa ++#define mmSDMA1_RLC6_WATERMARK_BASE_IDX 0 ++#define mmSDMA1_RLC6_DOORBELL_OFFSET 0x03ab ++#define mmSDMA1_RLC6_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC6_CSA_ADDR_LO 0x03ac ++#define mmSDMA1_RLC6_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC6_CSA_ADDR_HI 0x03ad ++#define mmSDMA1_RLC6_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC6_IB_SUB_REMAIN 0x03af ++#define mmSDMA1_RLC6_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA1_RLC6_PREEMPT 0x03b0 ++#define mmSDMA1_RLC6_PREEMPT_BASE_IDX 0 ++#define mmSDMA1_RLC6_DUMMY_REG 0x03b1 ++#define mmSDMA1_RLC6_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI 0x03b2 ++#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO 0x03b3 ++#define mmSDMA1_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC6_RB_AQL_CNTL 0x03b4 ++#define mmSDMA1_RLC6_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC6_MINOR_PTR_UPDATE 0x03b5 ++#define mmSDMA1_RLC6_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA1_RLC6_MIDCMD_DATA0 0x03c0 ++#define mmSDMA1_RLC6_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA1_RLC6_MIDCMD_DATA1 0x03c1 ++#define mmSDMA1_RLC6_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA1_RLC6_MIDCMD_DATA2 0x03c2 ++#define mmSDMA1_RLC6_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA1_RLC6_MIDCMD_DATA3 0x03c3 ++#define mmSDMA1_RLC6_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA1_RLC6_MIDCMD_DATA4 0x03c4 ++#define mmSDMA1_RLC6_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA1_RLC6_MIDCMD_DATA5 0x03c5 ++#define mmSDMA1_RLC6_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA1_RLC6_MIDCMD_DATA6 0x03c6 ++#define mmSDMA1_RLC6_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA1_RLC6_MIDCMD_DATA7 0x03c7 ++#define mmSDMA1_RLC6_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA1_RLC6_MIDCMD_DATA8 0x03c8 ++#define mmSDMA1_RLC6_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA1_RLC6_MIDCMD_CNTL 0x03c9 ++#define mmSDMA1_RLC6_MIDCMD_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC7_RB_CNTL 0x03e0 ++#define mmSDMA1_RLC7_RB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC7_RB_BASE 0x03e1 ++#define mmSDMA1_RLC7_RB_BASE_BASE_IDX 0 ++#define mmSDMA1_RLC7_RB_BASE_HI 0x03e2 ++#define mmSDMA1_RLC7_RB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC7_RB_RPTR 0x03e3 ++#define mmSDMA1_RLC7_RB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC7_RB_RPTR_HI 0x03e4 ++#define mmSDMA1_RLC7_RB_RPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC7_RB_WPTR 0x03e5 ++#define mmSDMA1_RLC7_RB_WPTR_BASE_IDX 0 ++#define mmSDMA1_RLC7_RB_WPTR_HI 0x03e6 ++#define mmSDMA1_RLC7_RB_WPTR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL 0x03e7 ++#define mmSDMA1_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC7_RB_RPTR_ADDR_HI 0x03e8 ++#define mmSDMA1_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC7_RB_RPTR_ADDR_LO 0x03e9 ++#define mmSDMA1_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC7_IB_CNTL 0x03ea ++#define mmSDMA1_RLC7_IB_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC7_IB_RPTR 0x03eb ++#define mmSDMA1_RLC7_IB_RPTR_BASE_IDX 0 ++#define mmSDMA1_RLC7_IB_OFFSET 0x03ec ++#define mmSDMA1_RLC7_IB_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC7_IB_BASE_LO 0x03ed ++#define mmSDMA1_RLC7_IB_BASE_LO_BASE_IDX 0 ++#define mmSDMA1_RLC7_IB_BASE_HI 0x03ee ++#define mmSDMA1_RLC7_IB_BASE_HI_BASE_IDX 0 ++#define mmSDMA1_RLC7_IB_SIZE 0x03ef ++#define mmSDMA1_RLC7_IB_SIZE_BASE_IDX 0 ++#define mmSDMA1_RLC7_SKIP_CNTL 0x03f0 ++#define mmSDMA1_RLC7_SKIP_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC7_CONTEXT_STATUS 0x03f1 ++#define mmSDMA1_RLC7_CONTEXT_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC7_DOORBELL 0x03f2 ++#define mmSDMA1_RLC7_DOORBELL_BASE_IDX 0 ++#define mmSDMA1_RLC7_STATUS 0x0408 ++#define mmSDMA1_RLC7_STATUS_BASE_IDX 0 ++#define mmSDMA1_RLC7_DOORBELL_LOG 0x0409 ++#define mmSDMA1_RLC7_DOORBELL_LOG_BASE_IDX 0 ++#define mmSDMA1_RLC7_WATERMARK 0x040a ++#define mmSDMA1_RLC7_WATERMARK_BASE_IDX 0 ++#define mmSDMA1_RLC7_DOORBELL_OFFSET 0x040b ++#define mmSDMA1_RLC7_DOORBELL_OFFSET_BASE_IDX 0 ++#define mmSDMA1_RLC7_CSA_ADDR_LO 0x040c ++#define mmSDMA1_RLC7_CSA_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC7_CSA_ADDR_HI 0x040d ++#define mmSDMA1_RLC7_CSA_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC7_IB_SUB_REMAIN 0x040f ++#define mmSDMA1_RLC7_IB_SUB_REMAIN_BASE_IDX 0 ++#define mmSDMA1_RLC7_PREEMPT 0x0410 ++#define mmSDMA1_RLC7_PREEMPT_BASE_IDX 0 ++#define mmSDMA1_RLC7_DUMMY_REG 0x0411 ++#define mmSDMA1_RLC7_DUMMY_REG_BASE_IDX 0 ++#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI 0x0412 ++#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 ++#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO 0x0413 ++#define mmSDMA1_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 ++#define mmSDMA1_RLC7_RB_AQL_CNTL 0x0414 ++#define mmSDMA1_RLC7_RB_AQL_CNTL_BASE_IDX 0 ++#define mmSDMA1_RLC7_MINOR_PTR_UPDATE 0x0415 ++#define mmSDMA1_RLC7_MINOR_PTR_UPDATE_BASE_IDX 0 ++#define mmSDMA1_RLC7_MIDCMD_DATA0 0x0420 ++#define mmSDMA1_RLC7_MIDCMD_DATA0_BASE_IDX 0 ++#define mmSDMA1_RLC7_MIDCMD_DATA1 0x0421 ++#define mmSDMA1_RLC7_MIDCMD_DATA1_BASE_IDX 0 ++#define mmSDMA1_RLC7_MIDCMD_DATA2 0x0422 ++#define mmSDMA1_RLC7_MIDCMD_DATA2_BASE_IDX 0 ++#define mmSDMA1_RLC7_MIDCMD_DATA3 0x0423 ++#define mmSDMA1_RLC7_MIDCMD_DATA3_BASE_IDX 0 ++#define mmSDMA1_RLC7_MIDCMD_DATA4 0x0424 ++#define mmSDMA1_RLC7_MIDCMD_DATA4_BASE_IDX 0 ++#define mmSDMA1_RLC7_MIDCMD_DATA5 0x0425 ++#define mmSDMA1_RLC7_MIDCMD_DATA5_BASE_IDX 0 ++#define mmSDMA1_RLC7_MIDCMD_DATA6 0x0426 ++#define mmSDMA1_RLC7_MIDCMD_DATA6_BASE_IDX 0 ++#define mmSDMA1_RLC7_MIDCMD_DATA7 0x0427 ++#define mmSDMA1_RLC7_MIDCMD_DATA7_BASE_IDX 0 ++#define mmSDMA1_RLC7_MIDCMD_DATA8 0x0428 ++#define mmSDMA1_RLC7_MIDCMD_DATA8_BASE_IDX 0 ++#define mmSDMA1_RLC7_MIDCMD_CNTL 0x0429 ++#define mmSDMA1_RLC7_MIDCMD_CNTL_BASE_IDX 0 ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h +new file mode 100644 +index 000000000000..0420ca583099 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_2_sh_mask.h +@@ -0,0 +1,2948 @@ ++/* ++ * Copyright (C) 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _sdma1_4_2_0_SH_MASK_HEADER ++#define _sdma1_4_2_0_SH_MASK_HEADER ++ ++ ++// addressBlock: sdma1_sdma1dec ++//SDMA1_UCODE_ADDR ++#define SDMA1_UCODE_ADDR__VALUE__SHIFT 0x0 ++#define SDMA1_UCODE_ADDR__VALUE_MASK 0x00001FFFL ++//SDMA1_UCODE_DATA ++#define SDMA1_UCODE_DATA__VALUE__SHIFT 0x0 ++#define SDMA1_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL ++//SDMA1_VM_CNTL ++#define SDMA1_VM_CNTL__CMD__SHIFT 0x0 ++#define SDMA1_VM_CNTL__CMD_MASK 0x0000000FL ++//SDMA1_VM_CTX_LO ++#define SDMA1_VM_CTX_LO__ADDR__SHIFT 0x2 ++#define SDMA1_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_VM_CTX_HI ++#define SDMA1_VM_CTX_HI__ADDR__SHIFT 0x0 ++#define SDMA1_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_ACTIVE_FCN_ID ++#define SDMA1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define SDMA1_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 ++#define SDMA1_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define SDMA1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL ++#define SDMA1_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L ++#define SDMA1_ACTIVE_FCN_ID__VF_MASK 0x80000000L ++//SDMA1_VM_CTX_CNTL ++#define SDMA1_VM_CTX_CNTL__PRIV__SHIFT 0x0 ++#define SDMA1_VM_CTX_CNTL__VMID__SHIFT 0x4 ++#define SDMA1_VM_CTX_CNTL__PRIV_MASK 0x00000001L ++#define SDMA1_VM_CTX_CNTL__VMID_MASK 0x000000F0L ++//SDMA1_VIRT_RESET_REQ ++#define SDMA1_VIRT_RESET_REQ__VF__SHIFT 0x0 ++#define SDMA1_VIRT_RESET_REQ__PF__SHIFT 0x1f ++#define SDMA1_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL ++#define SDMA1_VIRT_RESET_REQ__PF_MASK 0x80000000L ++//SDMA1_VF_ENABLE ++#define SDMA1_VF_ENABLE__VF_ENABLE__SHIFT 0x0 ++#define SDMA1_VF_ENABLE__VF_ENABLE_MASK 0x00000001L ++//SDMA1_CONTEXT_REG_TYPE0 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL__SHIFT 0x0 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE__SHIFT 0x1 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI__SHIFT 0x2 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR__SHIFT 0x3 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI__SHIFT 0x4 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR__SHIFT 0x5 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI__SHIFT 0x6 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL__SHIFT 0xa ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR__SHIFT 0xb ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET__SHIFT 0xc ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO__SHIFT 0xd ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI__SHIFT 0xe ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE__SHIFT 0xf ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL__SHIFT 0x10 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS__SHIFT 0x11 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL__SHIFT 0x12 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL__SHIFT 0x13 ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_CNTL_MASK 0x00000001L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_MASK 0x00000002L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_BASE_HI_MASK 0x00000004L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_MASK 0x00000008L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_HI_MASK 0x00000010L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_MASK 0x00000020L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_HI_MASK 0x00000040L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_CNTL_MASK 0x00000400L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_RPTR_MASK 0x00000800L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_OFFSET_MASK 0x00001000L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_LO_MASK 0x00002000L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_BASE_HI_MASK 0x00004000L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_IB_SIZE_MASK 0x00008000L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_SKIP_CNTL_MASK 0x00010000L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_STATUS_MASK 0x00020000L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_DOORBELL_MASK 0x00040000L ++#define SDMA1_CONTEXT_REG_TYPE0__SDMA1_GFX_CONTEXT_CNTL_MASK 0x00080000L ++//SDMA1_CONTEXT_REG_TYPE1 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS__SHIFT 0x8 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG__SHIFT 0x9 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK__SHIFT 0xa ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET__SHIFT 0xb ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO__SHIFT 0xc ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI__SHIFT 0xd ++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN__SHIFT 0xf ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT__SHIFT 0x10 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG__SHIFT 0x11 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL__SHIFT 0x14 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 ++#define SDMA1_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_STATUS_MASK 0x00000100L ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_LOG_MASK 0x00000200L ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_WATERMARK_MASK 0x00000400L ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DOORBELL_OFFSET_MASK 0x00000800L ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_LO_MASK 0x00001000L ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_CSA_ADDR_HI_MASK 0x00002000L ++#define SDMA1_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_IB_SUB_REMAIN_MASK 0x00008000L ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_PREEMPT_MASK 0x00010000L ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_DUMMY_REG_MASK 0x00020000L ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_RB_AQL_CNTL_MASK 0x00100000L ++#define SDMA1_CONTEXT_REG_TYPE1__SDMA1_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L ++#define SDMA1_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L ++//SDMA1_CONTEXT_REG_TYPE2 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0__SHIFT 0x0 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1__SHIFT 0x1 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2__SHIFT 0x2 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3__SHIFT 0x3 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4__SHIFT 0x4 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5__SHIFT 0x5 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6__SHIFT 0x6 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7__SHIFT 0x7 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8__SHIFT 0x8 ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL__SHIFT 0x9 ++#define SDMA1_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA0_MASK 0x00000001L ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA1_MASK 0x00000002L ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA2_MASK 0x00000004L ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA3_MASK 0x00000008L ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA4_MASK 0x00000010L ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA5_MASK 0x00000020L ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA6_MASK 0x00000040L ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA7_MASK 0x00000080L ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_DATA8_MASK 0x00000100L ++#define SDMA1_CONTEXT_REG_TYPE2__SDMA1_GFX_MIDCMD_CNTL_MASK 0x00000200L ++#define SDMA1_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L ++//SDMA1_CONTEXT_REG_TYPE3 ++#define SDMA1_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 ++#define SDMA1_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL ++//SDMA1_PUB_REG_TYPE0 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR__SHIFT 0x0 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA__SHIFT 0x1 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_REGISTER_SECURITY_CNTL__SHIFT 0x2 ++#define SDMA1_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL__SHIFT 0x4 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO__SHIFT 0x5 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI__SHIFT 0x6 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID__SHIFT 0x7 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL__SHIFT 0x8 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ__SHIFT 0x9 ++#define SDMA1_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0__SHIFT 0xb ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1__SHIFT 0xc ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2__SHIFT 0xd ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3__SHIFT 0xe ++#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0__SHIFT 0xf ++#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1__SHIFT 0x10 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2__SHIFT 0x11 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3__SHIFT 0x12 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL__SHIFT 0x13 ++#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 ++#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL__SHIFT 0x1a ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL__SHIFT 0x1b ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL__SHIFT 0x1c ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS__SHIFT 0x1d ++#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG__SHIFT 0x1e ++#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ__SHIFT 0x1f ++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_ADDR_MASK 0x00000001L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_UCODE_DATA_MASK 0x00000002L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_REGISTER_SECURITY_CNTL_MASK 0x00000004L ++#define SDMA1_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CNTL_MASK 0x00000010L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_LO_MASK 0x00000020L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_HI_MASK 0x00000040L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_ACTIVE_FCN_ID_MASK 0x00000080L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_VM_CTX_CNTL_MASK 0x00000100L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_VIRT_RESET_REQ_MASK 0x00000200L ++#define SDMA1_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE0_MASK 0x00000800L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE1_MASK 0x00001000L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE2_MASK 0x00002000L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_REG_TYPE3_MASK 0x00004000L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE0_MASK 0x00008000L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE1_MASK 0x00010000L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE2_MASK 0x00020000L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_PUB_REG_TYPE3_MASK 0x00040000L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_MMHUB_CNTL_MASK 0x00080000L ++#define SDMA1_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_POWER_CNTL_MASK 0x04000000L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CLK_CTRL_MASK 0x08000000L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CNTL_MASK 0x10000000L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_CHICKEN_BITS_MASK 0x20000000L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_MASK 0x40000000L ++#define SDMA1_PUB_REG_TYPE0__SDMA1_GB_ADDR_CONFIG_READ_MASK 0x80000000L ++//SDMA1_PUB_REG_TYPE1 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI__SHIFT 0x0 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH__SHIFT 0x2 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH__SHIFT 0x3 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM__SHIFT 0x4 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG__SHIFT 0x5 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG__SHIFT 0x6 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL__SHIFT 0x7 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG__SHIFT 0x8 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM__SHIFT 0x9 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL__SHIFT 0xa ++#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE__SHIFT 0xb ++#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM__SHIFT 0xc ++#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM__SHIFT 0xd ++#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe ++#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf ++#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 ++#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG__SHIFT 0x12 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD__SHIFT 0x13 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ID__SHIFT 0x14 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION__SHIFT 0x15 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER__SHIFT 0x16 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR__SHIFT 0x17 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG__SHIFT 0x18 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL__SHIFT 0x19 ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO__SHIFT 0x1a ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI__SHIFT 0x1b ++#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL__SHIFT 0x1c ++#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK__SHIFT 0x1d ++#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS__SHIFT 0x1e ++#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS__SHIFT 0x1f ++#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_HI_MASK 0x00000001L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_RB_RPTR_FETCH_MASK 0x00000004L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_IB_OFFSET_FETCH_MASK 0x00000008L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_PROGRAM_MASK 0x00000010L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS_REG_MASK 0x00000020L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS1_REG_MASK 0x00000040L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_RD_BURST_CNTL_MASK 0x00000080L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_HBM_PAGE_CONFIG_MASK 0x00000100L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_UCODE_CHECKSUM_MASK 0x00000200L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_F32_CNTL_MASK 0x00000400L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_FREEZE_MASK 0x00000800L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE0_QUANTUM_MASK 0x00001000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_PHASE1_QUANTUM_MASK 0x00002000L ++#define SDMA1_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L ++#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L ++#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L ++#define SDMA1_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_CONFIG_MASK 0x00040000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_BA_THRESHOLD_MASK 0x00080000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ID_MASK 0x00100000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_VERSION_MASK 0x00200000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_MASK 0x00400000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_EDC_COUNTER_CLEAR_MASK 0x00800000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_STATUS2_REG_MASK 0x01000000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_CNTL_MASK 0x02000000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_LO_MASK 0x04000000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_ATOMIC_PREOP_HI_MASK 0x08000000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_CNTL_MASK 0x10000000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WATERMK_MASK 0x20000000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_RD_STATUS_MASK 0x40000000L ++#define SDMA1_PUB_REG_TYPE1__SDMA1_UTCL1_WR_STATUS_MASK 0x80000000L ++//SDMA1_PUB_REG_TYPE2 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0__SHIFT 0x0 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1__SHIFT 0x1 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2__SHIFT 0x2 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0__SHIFT 0x3 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1__SHIFT 0x4 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0__SHIFT 0x5 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1__SHIFT 0x6 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT__SHIFT 0x7 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE__SHIFT 0x8 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE__SHIFT 0x9 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT__SHIFT 0xa ++#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2__SHIFT 0xb ++#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG__SHIFT 0xc ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO__SHIFT 0xd ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI__SHIFT 0xe ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM__SHIFT 0xf ++#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG__SHIFT 0x10 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0__SHIFT 0x11 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1__SHIFT 0x12 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2__SHIFT 0x13 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3__SHIFT 0x14 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER__SHIFT 0x15 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL__SHIFT 0x17 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT__SHIFT 0x18 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT__SHIFT 0x19 ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a ++#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL__SHIFT 0x1b ++#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d ++#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL__SHIFT 0x1e ++#define SDMA1_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV0_MASK 0x00000001L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV1_MASK 0x00000002L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_INV2_MASK 0x00000004L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK0_MASK 0x00000008L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_RD_XNACK1_MASK 0x00000010L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK0_MASK 0x00000020L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_WR_XNACK1_MASK 0x00000040L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_TIMEOUT_MASK 0x00000080L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_UTCL1_PAGE_MASK 0x00000100L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_POWER_CNTL_IDLE_MASK 0x00000200L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_RELAX_ORDERING_LUT_MASK 0x00000400L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_CHICKEN_BITS_2_MASK 0x00000800L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_STATUS3_REG_MASK 0x00001000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_LO_MASK 0x00002000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PHYSICAL_ADDR_HI_MASK 0x00004000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PHASE2_QUANTUM_MASK 0x00008000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_ERROR_LOG_MASK 0x00010000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG0_MASK 0x00020000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG1_MASK 0x00040000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG2_MASK 0x00080000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PUB_DUMMY_REG3_MASK 0x00100000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_F32_COUNTER_MASK 0x00200000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFMON_CNTL_MASK 0x00800000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER0_RESULT_MASK 0x01000000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER1_RESULT_MASK 0x02000000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_CRD_CNTL_MASK 0x08000000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L ++#define SDMA1_PUB_REG_TYPE2__SDMA1_ULV_CNTL_MASK 0x40000000L ++#define SDMA1_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L ++//SDMA1_PUB_REG_TYPE3 ++#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA__SHIFT 0x0 ++#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX__SHIFT 0x1 ++#define SDMA1_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 ++#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_DATA_MASK 0x00000001L ++#define SDMA1_PUB_REG_TYPE3__SDMA1_EA_DBIT_ADDR_INDEX_MASK 0x00000002L ++#define SDMA1_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL ++//SDMA1_MMHUB_CNTL ++#define SDMA1_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 ++#define SDMA1_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL ++//SDMA1_CONTEXT_GROUP_BOUNDARY ++#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 ++#define SDMA1_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL ++//SDMA1_POWER_CNTL ++#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 ++#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 ++#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa ++#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb ++#define SDMA1_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc ++#define SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L ++#define SDMA1_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L ++#define SDMA1_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L ++#define SDMA1_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L ++#define SDMA1_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L ++//SDMA1_CLK_CTRL ++#define SDMA1_CLK_CTRL__ON_DELAY__SHIFT 0x0 ++#define SDMA1_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 ++#define SDMA1_CLK_CTRL__RESERVED__SHIFT 0xc ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f ++#define SDMA1_CLK_CTRL__ON_DELAY_MASK 0x0000000FL ++#define SDMA1_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define SDMA1_CLK_CTRL__RESERVED_MASK 0x00FFF000L ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L ++#define SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L ++//SDMA1_CNTL ++#define SDMA1_CNTL__TRAP_ENABLE__SHIFT 0x0 ++#define SDMA1_CNTL__UTC_L1_ENABLE__SHIFT 0x1 ++#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 ++#define SDMA1_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 ++#define SDMA1_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 ++#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 ++#define SDMA1_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 ++#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c ++#define SDMA1_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d ++#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e ++#define SDMA1_CNTL__TRAP_ENABLE_MASK 0x00000001L ++#define SDMA1_CNTL__UTC_L1_ENABLE_MASK 0x00000002L ++#define SDMA1_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L ++#define SDMA1_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L ++#define SDMA1_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA1_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L ++#define SDMA1_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L ++#define SDMA1_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L ++#define SDMA1_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L ++#define SDMA1_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L ++#define SDMA1_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L ++//SDMA1_CHICKEN_BITS ++#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 ++#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 ++#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 ++#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 ++#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa ++#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 ++#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 ++#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 ++#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 ++#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 ++#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a ++#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c ++#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e ++#define SDMA1_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L ++#define SDMA1_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L ++#define SDMA1_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L ++#define SDMA1_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L ++#define SDMA1_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L ++#define SDMA1_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L ++#define SDMA1_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L ++#define SDMA1_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L ++#define SDMA1_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L ++#define SDMA1_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L ++#define SDMA1_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L ++#define SDMA1_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L ++#define SDMA1_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L ++//SDMA1_GB_ADDR_CONFIG ++#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 ++#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 ++#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 ++#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc ++#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 ++#define SDMA1_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L ++#define SDMA1_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L ++#define SDMA1_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L ++#define SDMA1_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L ++#define SDMA1_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L ++//SDMA1_GB_ADDR_CONFIG_READ ++#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 ++#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 ++#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 ++#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc ++#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 ++#define SDMA1_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L ++#define SDMA1_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L ++#define SDMA1_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L ++#define SDMA1_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L ++#define SDMA1_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L ++//SDMA1_RB_RPTR_FETCH_HI ++#define SDMA1_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_SEM_WAIT_FAIL_TIMER_CNTL ++#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 ++#define SDMA1_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL ++//SDMA1_RB_RPTR_FETCH ++#define SDMA1_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 ++#define SDMA1_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL ++//SDMA1_IB_OFFSET_FETCH ++#define SDMA1_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 ++#define SDMA1_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL ++//SDMA1_PROGRAM ++#define SDMA1_PROGRAM__STREAM__SHIFT 0x0 ++#define SDMA1_PROGRAM__STREAM_MASK 0xFFFFFFFFL ++//SDMA1_STATUS_REG ++#define SDMA1_STATUS_REG__IDLE__SHIFT 0x0 ++#define SDMA1_STATUS_REG__REG_IDLE__SHIFT 0x1 ++#define SDMA1_STATUS_REG__RB_EMPTY__SHIFT 0x2 ++#define SDMA1_STATUS_REG__RB_FULL__SHIFT 0x3 ++#define SDMA1_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 ++#define SDMA1_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 ++#define SDMA1_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 ++#define SDMA1_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 ++#define SDMA1_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 ++#define SDMA1_STATUS_REG__INSIDE_IB__SHIFT 0x9 ++#define SDMA1_STATUS_REG__EX_IDLE__SHIFT 0xa ++#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb ++#define SDMA1_STATUS_REG__PACKET_READY__SHIFT 0xc ++#define SDMA1_STATUS_REG__MC_WR_IDLE__SHIFT 0xd ++#define SDMA1_STATUS_REG__SRBM_IDLE__SHIFT 0xe ++#define SDMA1_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf ++#define SDMA1_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 ++#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 ++#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 ++#define SDMA1_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 ++#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 ++#define SDMA1_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 ++#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 ++#define SDMA1_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 ++#define SDMA1_STATUS_REG__SEM_IDLE__SHIFT 0x1a ++#define SDMA1_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b ++#define SDMA1_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c ++#define SDMA1_STATUS_REG__INT_IDLE__SHIFT 0x1e ++#define SDMA1_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f ++#define SDMA1_STATUS_REG__IDLE_MASK 0x00000001L ++#define SDMA1_STATUS_REG__REG_IDLE_MASK 0x00000002L ++#define SDMA1_STATUS_REG__RB_EMPTY_MASK 0x00000004L ++#define SDMA1_STATUS_REG__RB_FULL_MASK 0x00000008L ++#define SDMA1_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L ++#define SDMA1_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L ++#define SDMA1_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L ++#define SDMA1_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L ++#define SDMA1_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L ++#define SDMA1_STATUS_REG__INSIDE_IB_MASK 0x00000200L ++#define SDMA1_STATUS_REG__EX_IDLE_MASK 0x00000400L ++#define SDMA1_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L ++#define SDMA1_STATUS_REG__PACKET_READY_MASK 0x00001000L ++#define SDMA1_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L ++#define SDMA1_STATUS_REG__SRBM_IDLE_MASK 0x00004000L ++#define SDMA1_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L ++#define SDMA1_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L ++#define SDMA1_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L ++#define SDMA1_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L ++#define SDMA1_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L ++#define SDMA1_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L ++#define SDMA1_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L ++#define SDMA1_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L ++#define SDMA1_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L ++#define SDMA1_STATUS_REG__SEM_IDLE_MASK 0x04000000L ++#define SDMA1_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L ++#define SDMA1_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L ++#define SDMA1_STATUS_REG__INT_IDLE_MASK 0x40000000L ++#define SDMA1_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L ++//SDMA1_STATUS1_REG ++#define SDMA1_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 ++#define SDMA1_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 ++#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 ++#define SDMA1_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 ++#define SDMA1_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 ++#define SDMA1_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 ++#define SDMA1_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 ++#define SDMA1_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 ++#define SDMA1_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa ++#define SDMA1_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd ++#define SDMA1_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe ++#define SDMA1_STATUS1_REG__EX_START__SHIFT 0xf ++#define SDMA1_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 ++#define SDMA1_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 ++#define SDMA1_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L ++#define SDMA1_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L ++#define SDMA1_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L ++#define SDMA1_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L ++#define SDMA1_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L ++#define SDMA1_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L ++#define SDMA1_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L ++#define SDMA1_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L ++#define SDMA1_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L ++#define SDMA1_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L ++#define SDMA1_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L ++#define SDMA1_STATUS1_REG__EX_START_MASK 0x00008000L ++#define SDMA1_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L ++#define SDMA1_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L ++//SDMA1_RD_BURST_CNTL ++#define SDMA1_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 ++#define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST__SHIFT 0x2 ++#define SDMA1_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L ++#define SDMA1_RD_BURST_CNTL__CMD_BUFFER_RD_BURST_MASK 0x0000000CL ++//SDMA1_HBM_PAGE_CONFIG ++#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 ++#define SDMA1_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000001L ++//SDMA1_UCODE_CHECKSUM ++#define SDMA1_UCODE_CHECKSUM__DATA__SHIFT 0x0 ++#define SDMA1_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL ++//SDMA1_F32_CNTL ++#define SDMA1_F32_CNTL__HALT__SHIFT 0x0 ++#define SDMA1_F32_CNTL__STEP__SHIFT 0x1 ++#define SDMA1_F32_CNTL__HALT_MASK 0x00000001L ++#define SDMA1_F32_CNTL__STEP_MASK 0x00000002L ++//SDMA1_FREEZE ++#define SDMA1_FREEZE__PREEMPT__SHIFT 0x0 ++#define SDMA1_FREEZE__FREEZE__SHIFT 0x4 ++#define SDMA1_FREEZE__FROZEN__SHIFT 0x5 ++#define SDMA1_FREEZE__F32_FREEZE__SHIFT 0x6 ++#define SDMA1_FREEZE__PREEMPT_MASK 0x00000001L ++#define SDMA1_FREEZE__FREEZE_MASK 0x00000010L ++#define SDMA1_FREEZE__FROZEN_MASK 0x00000020L ++#define SDMA1_FREEZE__F32_FREEZE_MASK 0x00000040L ++//SDMA1_PHASE0_QUANTUM ++#define SDMA1_PHASE0_QUANTUM__UNIT__SHIFT 0x0 ++#define SDMA1_PHASE0_QUANTUM__VALUE__SHIFT 0x8 ++#define SDMA1_PHASE0_QUANTUM__PREFER__SHIFT 0x1e ++#define SDMA1_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL ++#define SDMA1_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L ++#define SDMA1_PHASE0_QUANTUM__PREFER_MASK 0x40000000L ++//SDMA1_PHASE1_QUANTUM ++#define SDMA1_PHASE1_QUANTUM__UNIT__SHIFT 0x0 ++#define SDMA1_PHASE1_QUANTUM__VALUE__SHIFT 0x8 ++#define SDMA1_PHASE1_QUANTUM__PREFER__SHIFT 0x1e ++#define SDMA1_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL ++#define SDMA1_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L ++#define SDMA1_PHASE1_QUANTUM__PREFER_MASK 0x40000000L ++//SDMA1_EDC_CONFIG ++#define SDMA1_EDC_CONFIG__DIS_EDC__SHIFT 0x1 ++#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 ++#define SDMA1_EDC_CONFIG__DIS_EDC_MASK 0x00000002L ++#define SDMA1_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L ++//SDMA1_BA_THRESHOLD ++#define SDMA1_BA_THRESHOLD__READ_THRES__SHIFT 0x0 ++#define SDMA1_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 ++#define SDMA1_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL ++#define SDMA1_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L ++//SDMA1_ID ++#define SDMA1_ID__DEVICE_ID__SHIFT 0x0 ++#define SDMA1_ID__DEVICE_ID_MASK 0x000000FFL ++//SDMA1_VERSION ++#define SDMA1_VERSION__MINVER__SHIFT 0x0 ++#define SDMA1_VERSION__MAJVER__SHIFT 0x8 ++#define SDMA1_VERSION__REV__SHIFT 0x10 ++#define SDMA1_VERSION__MINVER_MASK 0x0000007FL ++#define SDMA1_VERSION__MAJVER_MASK 0x00007F00L ++#define SDMA1_VERSION__REV_MASK 0x003F0000L ++//SDMA1_EDC_COUNTER ++#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SED__SHIFT 0x0 ++#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 ++#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 ++#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 ++#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 ++#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED__SHIFT 0xf ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED__SHIFT 0x10 ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED__SHIFT 0x11 ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED__SHIFT 0x12 ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED__SHIFT 0x13 ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED__SHIFT 0x14 ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED__SHIFT 0x15 ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED__SHIFT 0x16 ++#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0x17 ++#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x18 ++#define SDMA1_EDC_COUNTER__SDMA_UCODE_BUF_SED_MASK 0x00000001L ++#define SDMA1_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L ++#define SDMA1_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L ++#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L ++#define SDMA1_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L ++#define SDMA1_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF8_SED_MASK 0x00008000L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF9_SED_MASK 0x00010000L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF10_SED_MASK 0x00020000L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF11_SED_MASK 0x00040000L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF12_SED_MASK 0x00080000L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF13_SED_MASK 0x00100000L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF14_SED_MASK 0x00200000L ++#define SDMA1_EDC_COUNTER__SDMA_MBANK_DATA_BUF15_SED_MASK 0x00400000L ++#define SDMA1_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00800000L ++#define SDMA1_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x01000000L ++//SDMA1_EDC_COUNTER_CLEAR ++#define SDMA1_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 ++#define SDMA1_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L ++//SDMA1_STATUS2_REG ++#define SDMA1_STATUS2_REG__ID__SHIFT 0x0 ++#define SDMA1_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 ++#define SDMA1_STATUS2_REG__CMD_OP__SHIFT 0x10 ++#define SDMA1_STATUS2_REG__ID_MASK 0x00000003L ++#define SDMA1_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL ++#define SDMA1_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L ++//SDMA1_ATOMIC_CNTL ++#define SDMA1_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 ++#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f ++#define SDMA1_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL ++#define SDMA1_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L ++//SDMA1_ATOMIC_PREOP_LO ++#define SDMA1_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 ++#define SDMA1_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL ++//SDMA1_ATOMIC_PREOP_HI ++#define SDMA1_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 ++#define SDMA1_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL ++//SDMA1_UTCL1_CNTL ++#define SDMA1_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 ++#define SDMA1_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 ++#define SDMA1_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb ++#define SDMA1_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe ++#define SDMA1_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 ++#define SDMA1_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d ++#define SDMA1_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L ++#define SDMA1_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL ++#define SDMA1_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L ++#define SDMA1_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L ++#define SDMA1_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L ++#define SDMA1_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L ++//SDMA1_UTCL1_WATERMK ++#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 ++#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0x9 ++#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x11 ++#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x19 ++#define SDMA1_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000001FFL ++#define SDMA1_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0001FE00L ++#define SDMA1_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x01FE0000L ++#define SDMA1_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFE000000L ++//SDMA1_UTCL1_RD_STATUS ++#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 ++#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 ++#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 ++#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 ++#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 ++#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 ++#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 ++#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 ++#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 ++#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 ++#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa ++#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb ++#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc ++#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd ++#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe ++#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf ++#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 ++#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 ++#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 ++#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 ++#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 ++#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 ++#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 ++#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a ++#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d ++#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e ++#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f ++#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L ++#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L ++#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L ++#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L ++#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L ++#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L ++#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L ++#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L ++#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L ++#define SDMA1_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L ++#define SDMA1_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L ++#define SDMA1_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L ++#define SDMA1_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L ++#define SDMA1_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L ++#define SDMA1_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L ++#define SDMA1_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L ++#define SDMA1_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L ++#define SDMA1_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L ++#define SDMA1_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L ++#define SDMA1_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L ++#define SDMA1_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L ++#define SDMA1_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L ++#define SDMA1_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L ++#define SDMA1_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L ++#define SDMA1_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L ++#define SDMA1_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L ++#define SDMA1_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L ++//SDMA1_UTCL1_WR_STATUS ++#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 ++#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 ++#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 ++#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 ++#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 ++#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 ++#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 ++#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 ++#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 ++#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 ++#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa ++#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb ++#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc ++#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd ++#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe ++#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf ++#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 ++#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 ++#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 ++#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 ++#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 ++#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 ++#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 ++#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 ++#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c ++#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d ++#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e ++#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f ++#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L ++#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L ++#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L ++#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L ++#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L ++#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L ++#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L ++#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L ++#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L ++#define SDMA1_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L ++#define SDMA1_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L ++#define SDMA1_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L ++#define SDMA1_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L ++#define SDMA1_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L ++#define SDMA1_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L ++#define SDMA1_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L ++#define SDMA1_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L ++#define SDMA1_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L ++#define SDMA1_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L ++#define SDMA1_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L ++#define SDMA1_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L ++#define SDMA1_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L ++#define SDMA1_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L ++#define SDMA1_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L ++#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L ++#define SDMA1_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L ++#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L ++#define SDMA1_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L ++//SDMA1_UTCL1_INV0 ++#define SDMA1_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 ++#define SDMA1_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 ++#define SDMA1_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 ++#define SDMA1_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 ++#define SDMA1_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 ++#define SDMA1_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 ++#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 ++#define SDMA1_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 ++#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 ++#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 ++#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa ++#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb ++#define SDMA1_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc ++#define SDMA1_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c ++#define SDMA1_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L ++#define SDMA1_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L ++#define SDMA1_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L ++#define SDMA1_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L ++#define SDMA1_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L ++#define SDMA1_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L ++#define SDMA1_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L ++#define SDMA1_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L ++#define SDMA1_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L ++#define SDMA1_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L ++#define SDMA1_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L ++#define SDMA1_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L ++#define SDMA1_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L ++#define SDMA1_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L ++//SDMA1_UTCL1_INV1 ++#define SDMA1_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 ++#define SDMA1_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL ++//SDMA1_UTCL1_INV2 ++#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 ++#define SDMA1_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL ++//SDMA1_UTCL1_RD_XNACK0 ++#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 ++#define SDMA1_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL ++//SDMA1_UTCL1_RD_XNACK1 ++#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 ++#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 ++#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 ++#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a ++#define SDMA1_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL ++#define SDMA1_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L ++#define SDMA1_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L ++#define SDMA1_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L ++//SDMA1_UTCL1_WR_XNACK0 ++#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 ++#define SDMA1_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL ++//SDMA1_UTCL1_WR_XNACK1 ++#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 ++#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 ++#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 ++#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a ++#define SDMA1_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL ++#define SDMA1_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L ++#define SDMA1_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L ++#define SDMA1_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L ++//SDMA1_UTCL1_TIMEOUT ++#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 ++#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 ++#define SDMA1_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL ++#define SDMA1_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L ++//SDMA1_UTCL1_PAGE ++#define SDMA1_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 ++#define SDMA1_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 ++#define SDMA1_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 ++#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 ++#define SDMA1_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L ++#define SDMA1_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL ++#define SDMA1_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L ++#define SDMA1_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L ++//SDMA1_POWER_CNTL_IDLE ++#define SDMA1_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 ++#define SDMA1_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 ++#define SDMA1_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 ++#define SDMA1_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL ++#define SDMA1_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L ++#define SDMA1_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L ++//SDMA1_RELAX_ORDERING_LUT ++#define SDMA1_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 ++#define SDMA1_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 ++#define SDMA1_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 ++#define SDMA1_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 ++#define SDMA1_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 ++#define SDMA1_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 ++#define SDMA1_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 ++#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 ++#define SDMA1_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 ++#define SDMA1_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa ++#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb ++#define SDMA1_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc ++#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd ++#define SDMA1_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe ++#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b ++#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c ++#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d ++#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e ++#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f ++#define SDMA1_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L ++#define SDMA1_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L ++#define SDMA1_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L ++#define SDMA1_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L ++#define SDMA1_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L ++#define SDMA1_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L ++#define SDMA1_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L ++#define SDMA1_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L ++#define SDMA1_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L ++#define SDMA1_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L ++#define SDMA1_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L ++#define SDMA1_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L ++#define SDMA1_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L ++#define SDMA1_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L ++#define SDMA1_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L ++#define SDMA1_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L ++#define SDMA1_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L ++#define SDMA1_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L ++#define SDMA1_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L ++//SDMA1_CHICKEN_BITS_2 ++#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 ++#define SDMA1_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL ++//SDMA1_STATUS3_REG ++#define SDMA1_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 ++#define SDMA1_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 ++#define SDMA1_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 ++#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x15 ++#define SDMA1_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x16 ++#define SDMA1_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL ++#define SDMA1_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L ++#define SDMA1_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L ++#define SDMA1_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x00200000L ++#define SDMA1_STATUS3_REG__INT_QUEUE_ID_MASK 0x03C00000L ++//SDMA1_PHYSICAL_ADDR_LO ++#define SDMA1_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 ++#define SDMA1_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 ++#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 ++#define SDMA1_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc ++#define SDMA1_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L ++#define SDMA1_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L ++#define SDMA1_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L ++#define SDMA1_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L ++//SDMA1_PHYSICAL_ADDR_HI ++#define SDMA1_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL ++//SDMA1_PHASE2_QUANTUM ++#define SDMA1_PHASE2_QUANTUM__UNIT__SHIFT 0x0 ++#define SDMA1_PHASE2_QUANTUM__VALUE__SHIFT 0x8 ++#define SDMA1_PHASE2_QUANTUM__PREFER__SHIFT 0x1e ++#define SDMA1_PHASE2_QUANTUM__UNIT_MASK 0x0000000FL ++#define SDMA1_PHASE2_QUANTUM__VALUE_MASK 0x00FFFF00L ++#define SDMA1_PHASE2_QUANTUM__PREFER_MASK 0x40000000L ++//SDMA1_ERROR_LOG ++#define SDMA1_ERROR_LOG__OVERRIDE__SHIFT 0x0 ++#define SDMA1_ERROR_LOG__STATUS__SHIFT 0x10 ++#define SDMA1_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL ++#define SDMA1_ERROR_LOG__STATUS_MASK 0xFFFF0000L ++//SDMA1_PUB_DUMMY_REG0 ++#define SDMA1_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 ++#define SDMA1_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL ++//SDMA1_PUB_DUMMY_REG1 ++#define SDMA1_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 ++#define SDMA1_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL ++//SDMA1_PUB_DUMMY_REG2 ++#define SDMA1_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 ++#define SDMA1_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL ++//SDMA1_PUB_DUMMY_REG3 ++#define SDMA1_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 ++#define SDMA1_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL ++//SDMA1_F32_COUNTER ++#define SDMA1_F32_COUNTER__VALUE__SHIFT 0x0 ++#define SDMA1_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL ++//SDMA1_PERFMON_CNTL ++#define SDMA1_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 ++#define SDMA1_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 ++#define SDMA1_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 ++#define SDMA1_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa ++#define SDMA1_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb ++#define SDMA1_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc ++#define SDMA1_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L ++#define SDMA1_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L ++#define SDMA1_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL ++#define SDMA1_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L ++#define SDMA1_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L ++#define SDMA1_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L ++//SDMA1_PERFCOUNTER0_RESULT ++#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 ++#define SDMA1_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL ++//SDMA1_PERFCOUNTER1_RESULT ++#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 ++#define SDMA1_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL ++//SDMA1_PERFCOUNTER_TAG_DELAY_RANGE ++#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 ++#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe ++#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c ++#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL ++#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L ++#define SDMA1_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L ++//SDMA1_CRD_CNTL ++#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 ++#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd ++#define SDMA1_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L ++#define SDMA1_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L ++//SDMA1_GPU_IOV_VIOLATION_LOG ++#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 ++#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 ++#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 ++#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 ++#define SDMA1_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 ++#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 ++#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 ++#define SDMA1_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L ++#define SDMA1_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L ++#define SDMA1_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL ++#define SDMA1_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L ++#define SDMA1_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L ++#define SDMA1_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L ++#define SDMA1_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L ++//SDMA1_ULV_CNTL ++#define SDMA1_ULV_CNTL__HYSTERESIS__SHIFT 0x0 ++#define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR__SHIFT 0x1b ++#define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR__SHIFT 0x1c ++#define SDMA1_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d ++#define SDMA1_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e ++#define SDMA1_ULV_CNTL__ULV_STATUS__SHIFT 0x1f ++#define SDMA1_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL ++#define SDMA1_ULV_CNTL__ENTER_ULV_INT_CLR_MASK 0x08000000L ++#define SDMA1_ULV_CNTL__EXIT_ULV_INT_CLR_MASK 0x10000000L ++#define SDMA1_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L ++#define SDMA1_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L ++#define SDMA1_ULV_CNTL__ULV_STATUS_MASK 0x80000000L ++//SDMA1_EA_DBIT_ADDR_DATA ++#define SDMA1_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 ++#define SDMA1_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL ++//SDMA1_EA_DBIT_ADDR_INDEX ++#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 ++#define SDMA1_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L ++//SDMA1_GFX_RB_CNTL ++#define SDMA1_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA1_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA1_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA1_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA1_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA1_GFX_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA1_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA1_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA1_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA1_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA1_GFX_RB_BASE ++#define SDMA1_GFX_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA1_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_GFX_RB_BASE_HI ++#define SDMA1_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA1_GFX_RB_RPTR ++#define SDMA1_GFX_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_GFX_RB_RPTR_HI ++#define SDMA1_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_GFX_RB_WPTR ++#define SDMA1_GFX_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_GFX_RB_WPTR_HI ++#define SDMA1_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_GFX_RB_WPTR_POLL_CNTL ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA1_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA1_GFX_RB_RPTR_ADDR_HI ++#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_GFX_RB_RPTR_ADDR_LO ++#define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_GFX_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA1_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_GFX_IB_CNTL ++#define SDMA1_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA1_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA1_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA1_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA1_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA1_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA1_GFX_IB_RPTR ++#define SDMA1_GFX_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA1_GFX_IB_OFFSET ++#define SDMA1_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA1_GFX_IB_BASE_LO ++#define SDMA1_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA1_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA1_GFX_IB_BASE_HI ++#define SDMA1_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_GFX_IB_SIZE ++#define SDMA1_GFX_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA1_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA1_GFX_SKIP_CNTL ++#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA1_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA1_GFX_CONTEXT_STATUS ++#define SDMA1_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA1_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA1_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA1_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA1_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA1_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA1_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA1_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA1_GFX_DOORBELL ++#define SDMA1_GFX_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA1_GFX_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA1_GFX_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA1_GFX_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA1_GFX_CONTEXT_CNTL ++#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 ++#define SDMA1_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L ++//SDMA1_GFX_STATUS ++#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA1_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA1_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA1_GFX_DOORBELL_LOG ++#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA1_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA1_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA1_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA1_GFX_WATERMARK ++#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA1_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA1_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA1_GFX_DOORBELL_OFFSET ++#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA1_GFX_CSA_ADDR_LO ++#define SDMA1_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_GFX_CSA_ADDR_HI ++#define SDMA1_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_GFX_IB_SUB_REMAIN ++#define SDMA1_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA1_GFX_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA1_GFX_PREEMPT ++#define SDMA1_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA1_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA1_GFX_DUMMY_REG ++#define SDMA1_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA1_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA1_GFX_RB_WPTR_POLL_ADDR_HI ++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_GFX_RB_WPTR_POLL_ADDR_LO ++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_GFX_RB_AQL_CNTL ++#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA1_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA1_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA1_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA1_GFX_MINOR_PTR_UPDATE ++#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA1_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA1_GFX_MIDCMD_DATA0 ++#define SDMA1_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA1_GFX_MIDCMD_DATA1 ++#define SDMA1_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA1_GFX_MIDCMD_DATA2 ++#define SDMA1_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA1_GFX_MIDCMD_DATA3 ++#define SDMA1_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA1_GFX_MIDCMD_DATA4 ++#define SDMA1_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA1_GFX_MIDCMD_DATA5 ++#define SDMA1_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA1_GFX_MIDCMD_DATA6 ++#define SDMA1_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA1_GFX_MIDCMD_DATA7 ++#define SDMA1_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA1_GFX_MIDCMD_DATA8 ++#define SDMA1_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA1_GFX_MIDCMD_CNTL ++#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA1_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA1_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA1_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA1_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA1_PAGE_RB_CNTL ++#define SDMA1_PAGE_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA1_PAGE_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA1_PAGE_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA1_PAGE_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA1_PAGE_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA1_PAGE_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA1_PAGE_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA1_PAGE_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA1_PAGE_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA1_PAGE_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA1_PAGE_RB_BASE ++#define SDMA1_PAGE_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA1_PAGE_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_RB_BASE_HI ++#define SDMA1_PAGE_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_PAGE_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA1_PAGE_RB_RPTR ++#define SDMA1_PAGE_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_PAGE_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_RB_RPTR_HI ++#define SDMA1_PAGE_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_PAGE_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_RB_WPTR ++#define SDMA1_PAGE_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_PAGE_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_RB_WPTR_HI ++#define SDMA1_PAGE_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_PAGE_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_RB_WPTR_POLL_CNTL ++#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA1_PAGE_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA1_PAGE_RB_RPTR_ADDR_HI ++#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_PAGE_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_RB_RPTR_ADDR_LO ++#define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_PAGE_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA1_PAGE_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_PAGE_IB_CNTL ++#define SDMA1_PAGE_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA1_PAGE_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA1_PAGE_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA1_PAGE_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA1_PAGE_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA1_PAGE_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA1_PAGE_IB_RPTR ++#define SDMA1_PAGE_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_PAGE_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA1_PAGE_IB_OFFSET ++#define SDMA1_PAGE_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_PAGE_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA1_PAGE_IB_BASE_LO ++#define SDMA1_PAGE_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA1_PAGE_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA1_PAGE_IB_BASE_HI ++#define SDMA1_PAGE_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_PAGE_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_IB_SIZE ++#define SDMA1_PAGE_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA1_PAGE_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA1_PAGE_SKIP_CNTL ++#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA1_PAGE_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA1_PAGE_CONTEXT_STATUS ++#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA1_PAGE_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA1_PAGE_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA1_PAGE_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA1_PAGE_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA1_PAGE_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA1_PAGE_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA1_PAGE_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA1_PAGE_DOORBELL ++#define SDMA1_PAGE_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA1_PAGE_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA1_PAGE_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA1_PAGE_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA1_PAGE_STATUS ++#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA1_PAGE_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA1_PAGE_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA1_PAGE_DOORBELL_LOG ++#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA1_PAGE_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA1_PAGE_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA1_PAGE_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA1_PAGE_WATERMARK ++#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA1_PAGE_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA1_PAGE_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA1_PAGE_DOORBELL_OFFSET ++#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_PAGE_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA1_PAGE_CSA_ADDR_LO ++#define SDMA1_PAGE_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_PAGE_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_PAGE_CSA_ADDR_HI ++#define SDMA1_PAGE_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_PAGE_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_IB_SUB_REMAIN ++#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA1_PAGE_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA1_PAGE_PREEMPT ++#define SDMA1_PAGE_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA1_PAGE_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA1_PAGE_DUMMY_REG ++#define SDMA1_PAGE_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA1_PAGE_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI ++#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO ++#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_PAGE_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_PAGE_RB_AQL_CNTL ++#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA1_PAGE_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA1_PAGE_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA1_PAGE_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA1_PAGE_MINOR_PTR_UPDATE ++#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA1_PAGE_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA1_PAGE_MIDCMD_DATA0 ++#define SDMA1_PAGE_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA1_PAGE_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_MIDCMD_DATA1 ++#define SDMA1_PAGE_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA1_PAGE_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_MIDCMD_DATA2 ++#define SDMA1_PAGE_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA1_PAGE_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_MIDCMD_DATA3 ++#define SDMA1_PAGE_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA1_PAGE_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_MIDCMD_DATA4 ++#define SDMA1_PAGE_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA1_PAGE_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_MIDCMD_DATA5 ++#define SDMA1_PAGE_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA1_PAGE_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_MIDCMD_DATA6 ++#define SDMA1_PAGE_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA1_PAGE_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_MIDCMD_DATA7 ++#define SDMA1_PAGE_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA1_PAGE_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_MIDCMD_DATA8 ++#define SDMA1_PAGE_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA1_PAGE_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA1_PAGE_MIDCMD_CNTL ++#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA1_PAGE_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA1_PAGE_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA1_PAGE_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA1_PAGE_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA1_RLC0_RB_CNTL ++#define SDMA1_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA1_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA1_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA1_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA1_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA1_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA1_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA1_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA1_RLC0_RB_BASE ++#define SDMA1_RLC0_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA1_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_RB_BASE_HI ++#define SDMA1_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA1_RLC0_RB_RPTR ++#define SDMA1_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_RB_RPTR_HI ++#define SDMA1_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_RB_WPTR ++#define SDMA1_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_RB_WPTR_HI ++#define SDMA1_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_RB_WPTR_POLL_CNTL ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA1_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA1_RLC0_RB_RPTR_ADDR_HI ++#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_RB_RPTR_ADDR_LO ++#define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC0_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA1_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC0_IB_CNTL ++#define SDMA1_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA1_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA1_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA1_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA1_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA1_RLC0_IB_RPTR ++#define SDMA1_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC0_IB_OFFSET ++#define SDMA1_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC0_IB_BASE_LO ++#define SDMA1_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA1_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA1_RLC0_IB_BASE_HI ++#define SDMA1_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_IB_SIZE ++#define SDMA1_RLC0_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA1_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC0_SKIP_CNTL ++#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA1_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA1_RLC0_CONTEXT_STATUS ++#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA1_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA1_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA1_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA1_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA1_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA1_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA1_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA1_RLC0_DOORBELL ++#define SDMA1_RLC0_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA1_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA1_RLC0_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA1_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA1_RLC0_STATUS ++#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA1_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA1_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA1_RLC0_DOORBELL_LOG ++#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA1_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA1_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA1_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA1_RLC0_WATERMARK ++#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA1_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA1_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA1_RLC0_DOORBELL_OFFSET ++#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA1_RLC0_CSA_ADDR_LO ++#define SDMA1_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC0_CSA_ADDR_HI ++#define SDMA1_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_IB_SUB_REMAIN ++#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA1_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC0_PREEMPT ++#define SDMA1_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA1_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA1_RLC0_DUMMY_REG ++#define SDMA1_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA1_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI ++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO ++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC0_RB_AQL_CNTL ++#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA1_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA1_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA1_RLC0_MINOR_PTR_UPDATE ++#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA1_RLC0_MIDCMD_DATA0 ++#define SDMA1_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_MIDCMD_DATA1 ++#define SDMA1_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_MIDCMD_DATA2 ++#define SDMA1_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_MIDCMD_DATA3 ++#define SDMA1_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_MIDCMD_DATA4 ++#define SDMA1_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_MIDCMD_DATA5 ++#define SDMA1_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_MIDCMD_DATA6 ++#define SDMA1_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_MIDCMD_DATA7 ++#define SDMA1_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_MIDCMD_DATA8 ++#define SDMA1_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA1_RLC0_MIDCMD_CNTL ++#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA1_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA1_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA1_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA1_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA1_RLC1_RB_CNTL ++#define SDMA1_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA1_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA1_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA1_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA1_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA1_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA1_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA1_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA1_RLC1_RB_BASE ++#define SDMA1_RLC1_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA1_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_RB_BASE_HI ++#define SDMA1_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA1_RLC1_RB_RPTR ++#define SDMA1_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_RB_RPTR_HI ++#define SDMA1_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_RB_WPTR ++#define SDMA1_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_RB_WPTR_HI ++#define SDMA1_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_RB_WPTR_POLL_CNTL ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA1_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA1_RLC1_RB_RPTR_ADDR_HI ++#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_RB_RPTR_ADDR_LO ++#define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC1_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA1_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC1_IB_CNTL ++#define SDMA1_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA1_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA1_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA1_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA1_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA1_RLC1_IB_RPTR ++#define SDMA1_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC1_IB_OFFSET ++#define SDMA1_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC1_IB_BASE_LO ++#define SDMA1_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA1_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA1_RLC1_IB_BASE_HI ++#define SDMA1_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_IB_SIZE ++#define SDMA1_RLC1_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA1_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC1_SKIP_CNTL ++#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA1_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA1_RLC1_CONTEXT_STATUS ++#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA1_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA1_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA1_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA1_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA1_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA1_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA1_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA1_RLC1_DOORBELL ++#define SDMA1_RLC1_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA1_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA1_RLC1_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA1_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA1_RLC1_STATUS ++#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA1_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA1_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA1_RLC1_DOORBELL_LOG ++#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA1_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA1_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA1_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA1_RLC1_WATERMARK ++#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA1_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA1_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA1_RLC1_DOORBELL_OFFSET ++#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA1_RLC1_CSA_ADDR_LO ++#define SDMA1_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC1_CSA_ADDR_HI ++#define SDMA1_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_IB_SUB_REMAIN ++#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA1_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC1_PREEMPT ++#define SDMA1_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA1_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA1_RLC1_DUMMY_REG ++#define SDMA1_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA1_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI ++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO ++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC1_RB_AQL_CNTL ++#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA1_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA1_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA1_RLC1_MINOR_PTR_UPDATE ++#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA1_RLC1_MIDCMD_DATA0 ++#define SDMA1_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_MIDCMD_DATA1 ++#define SDMA1_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_MIDCMD_DATA2 ++#define SDMA1_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_MIDCMD_DATA3 ++#define SDMA1_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_MIDCMD_DATA4 ++#define SDMA1_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_MIDCMD_DATA5 ++#define SDMA1_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_MIDCMD_DATA6 ++#define SDMA1_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_MIDCMD_DATA7 ++#define SDMA1_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_MIDCMD_DATA8 ++#define SDMA1_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA1_RLC1_MIDCMD_CNTL ++#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA1_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA1_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA1_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA1_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA1_RLC2_RB_CNTL ++#define SDMA1_RLC2_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC2_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA1_RLC2_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA1_RLC2_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA1_RLC2_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC2_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA1_RLC2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA1_RLC2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA1_RLC2_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA1_RLC2_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA1_RLC2_RB_BASE ++#define SDMA1_RLC2_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA1_RLC2_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_RB_BASE_HI ++#define SDMA1_RLC2_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA1_RLC2_RB_RPTR ++#define SDMA1_RLC2_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_RB_RPTR_HI ++#define SDMA1_RLC2_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_RB_WPTR ++#define SDMA1_RLC2_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_RB_WPTR_HI ++#define SDMA1_RLC2_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_RB_WPTR_POLL_CNTL ++#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA1_RLC2_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA1_RLC2_RB_RPTR_ADDR_HI ++#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_RB_RPTR_ADDR_LO ++#define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC2_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA1_RLC2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC2_IB_CNTL ++#define SDMA1_RLC2_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA1_RLC2_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA1_RLC2_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA1_RLC2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA1_RLC2_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA1_RLC2_IB_RPTR ++#define SDMA1_RLC2_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC2_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC2_IB_OFFSET ++#define SDMA1_RLC2_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC2_IB_BASE_LO ++#define SDMA1_RLC2_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA1_RLC2_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA1_RLC2_IB_BASE_HI ++#define SDMA1_RLC2_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_IB_SIZE ++#define SDMA1_RLC2_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA1_RLC2_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC2_SKIP_CNTL ++#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA1_RLC2_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA1_RLC2_CONTEXT_STATUS ++#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA1_RLC2_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA1_RLC2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA1_RLC2_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA1_RLC2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA1_RLC2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA1_RLC2_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA1_RLC2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA1_RLC2_DOORBELL ++#define SDMA1_RLC2_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA1_RLC2_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA1_RLC2_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA1_RLC2_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA1_RLC2_STATUS ++#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA1_RLC2_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA1_RLC2_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA1_RLC2_DOORBELL_LOG ++#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA1_RLC2_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA1_RLC2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA1_RLC2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA1_RLC2_WATERMARK ++#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA1_RLC2_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA1_RLC2_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA1_RLC2_DOORBELL_OFFSET ++#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA1_RLC2_CSA_ADDR_LO ++#define SDMA1_RLC2_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC2_CSA_ADDR_HI ++#define SDMA1_RLC2_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_IB_SUB_REMAIN ++#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA1_RLC2_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC2_PREEMPT ++#define SDMA1_RLC2_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA1_RLC2_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA1_RLC2_DUMMY_REG ++#define SDMA1_RLC2_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA1_RLC2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI ++#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO ++#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC2_RB_AQL_CNTL ++#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA1_RLC2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA1_RLC2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA1_RLC2_MINOR_PTR_UPDATE ++#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA1_RLC2_MIDCMD_DATA0 ++#define SDMA1_RLC2_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA1_RLC2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_MIDCMD_DATA1 ++#define SDMA1_RLC2_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA1_RLC2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_MIDCMD_DATA2 ++#define SDMA1_RLC2_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA1_RLC2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_MIDCMD_DATA3 ++#define SDMA1_RLC2_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA1_RLC2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_MIDCMD_DATA4 ++#define SDMA1_RLC2_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA1_RLC2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_MIDCMD_DATA5 ++#define SDMA1_RLC2_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA1_RLC2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_MIDCMD_DATA6 ++#define SDMA1_RLC2_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA1_RLC2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_MIDCMD_DATA7 ++#define SDMA1_RLC2_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA1_RLC2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_MIDCMD_DATA8 ++#define SDMA1_RLC2_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA1_RLC2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA1_RLC2_MIDCMD_CNTL ++#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA1_RLC2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA1_RLC2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA1_RLC2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA1_RLC2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA1_RLC3_RB_CNTL ++#define SDMA1_RLC3_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC3_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA1_RLC3_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA1_RLC3_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA1_RLC3_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC3_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA1_RLC3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA1_RLC3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA1_RLC3_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA1_RLC3_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA1_RLC3_RB_BASE ++#define SDMA1_RLC3_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA1_RLC3_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_RB_BASE_HI ++#define SDMA1_RLC3_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA1_RLC3_RB_RPTR ++#define SDMA1_RLC3_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_RB_RPTR_HI ++#define SDMA1_RLC3_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_RB_WPTR ++#define SDMA1_RLC3_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_RB_WPTR_HI ++#define SDMA1_RLC3_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_RB_WPTR_POLL_CNTL ++#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA1_RLC3_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA1_RLC3_RB_RPTR_ADDR_HI ++#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_RB_RPTR_ADDR_LO ++#define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC3_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA1_RLC3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC3_IB_CNTL ++#define SDMA1_RLC3_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA1_RLC3_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA1_RLC3_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA1_RLC3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA1_RLC3_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA1_RLC3_IB_RPTR ++#define SDMA1_RLC3_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC3_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC3_IB_OFFSET ++#define SDMA1_RLC3_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC3_IB_BASE_LO ++#define SDMA1_RLC3_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA1_RLC3_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA1_RLC3_IB_BASE_HI ++#define SDMA1_RLC3_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_IB_SIZE ++#define SDMA1_RLC3_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA1_RLC3_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC3_SKIP_CNTL ++#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA1_RLC3_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA1_RLC3_CONTEXT_STATUS ++#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA1_RLC3_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA1_RLC3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA1_RLC3_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA1_RLC3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA1_RLC3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA1_RLC3_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA1_RLC3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA1_RLC3_DOORBELL ++#define SDMA1_RLC3_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA1_RLC3_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA1_RLC3_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA1_RLC3_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA1_RLC3_STATUS ++#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA1_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA1_RLC3_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA1_RLC3_DOORBELL_LOG ++#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA1_RLC3_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA1_RLC3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA1_RLC3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA1_RLC3_WATERMARK ++#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA1_RLC3_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA1_RLC3_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA1_RLC3_DOORBELL_OFFSET ++#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA1_RLC3_CSA_ADDR_LO ++#define SDMA1_RLC3_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC3_CSA_ADDR_HI ++#define SDMA1_RLC3_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_IB_SUB_REMAIN ++#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA1_RLC3_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC3_PREEMPT ++#define SDMA1_RLC3_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA1_RLC3_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA1_RLC3_DUMMY_REG ++#define SDMA1_RLC3_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA1_RLC3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI ++#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO ++#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC3_RB_AQL_CNTL ++#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA1_RLC3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA1_RLC3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA1_RLC3_MINOR_PTR_UPDATE ++#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA1_RLC3_MIDCMD_DATA0 ++#define SDMA1_RLC3_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA1_RLC3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_MIDCMD_DATA1 ++#define SDMA1_RLC3_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA1_RLC3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_MIDCMD_DATA2 ++#define SDMA1_RLC3_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA1_RLC3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_MIDCMD_DATA3 ++#define SDMA1_RLC3_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA1_RLC3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_MIDCMD_DATA4 ++#define SDMA1_RLC3_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA1_RLC3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_MIDCMD_DATA5 ++#define SDMA1_RLC3_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA1_RLC3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_MIDCMD_DATA6 ++#define SDMA1_RLC3_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA1_RLC3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_MIDCMD_DATA7 ++#define SDMA1_RLC3_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA1_RLC3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_MIDCMD_DATA8 ++#define SDMA1_RLC3_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA1_RLC3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA1_RLC3_MIDCMD_CNTL ++#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA1_RLC3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA1_RLC3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA1_RLC3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA1_RLC3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA1_RLC4_RB_CNTL ++#define SDMA1_RLC4_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC4_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA1_RLC4_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA1_RLC4_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA1_RLC4_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC4_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA1_RLC4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA1_RLC4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA1_RLC4_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA1_RLC4_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA1_RLC4_RB_BASE ++#define SDMA1_RLC4_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA1_RLC4_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_RB_BASE_HI ++#define SDMA1_RLC4_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA1_RLC4_RB_RPTR ++#define SDMA1_RLC4_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_RB_RPTR_HI ++#define SDMA1_RLC4_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_RB_WPTR ++#define SDMA1_RLC4_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_RB_WPTR_HI ++#define SDMA1_RLC4_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_RB_WPTR_POLL_CNTL ++#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA1_RLC4_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA1_RLC4_RB_RPTR_ADDR_HI ++#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_RB_RPTR_ADDR_LO ++#define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC4_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA1_RLC4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC4_IB_CNTL ++#define SDMA1_RLC4_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA1_RLC4_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA1_RLC4_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA1_RLC4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA1_RLC4_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA1_RLC4_IB_RPTR ++#define SDMA1_RLC4_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC4_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC4_IB_OFFSET ++#define SDMA1_RLC4_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC4_IB_BASE_LO ++#define SDMA1_RLC4_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA1_RLC4_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA1_RLC4_IB_BASE_HI ++#define SDMA1_RLC4_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_IB_SIZE ++#define SDMA1_RLC4_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA1_RLC4_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC4_SKIP_CNTL ++#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA1_RLC4_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA1_RLC4_CONTEXT_STATUS ++#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA1_RLC4_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA1_RLC4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA1_RLC4_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA1_RLC4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA1_RLC4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA1_RLC4_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA1_RLC4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA1_RLC4_DOORBELL ++#define SDMA1_RLC4_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA1_RLC4_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA1_RLC4_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA1_RLC4_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA1_RLC4_STATUS ++#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA1_RLC4_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA1_RLC4_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA1_RLC4_DOORBELL_LOG ++#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA1_RLC4_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA1_RLC4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA1_RLC4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA1_RLC4_WATERMARK ++#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA1_RLC4_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA1_RLC4_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA1_RLC4_DOORBELL_OFFSET ++#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA1_RLC4_CSA_ADDR_LO ++#define SDMA1_RLC4_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC4_CSA_ADDR_HI ++#define SDMA1_RLC4_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_IB_SUB_REMAIN ++#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA1_RLC4_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC4_PREEMPT ++#define SDMA1_RLC4_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA1_RLC4_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA1_RLC4_DUMMY_REG ++#define SDMA1_RLC4_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA1_RLC4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI ++#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO ++#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC4_RB_AQL_CNTL ++#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA1_RLC4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA1_RLC4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA1_RLC4_MINOR_PTR_UPDATE ++#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA1_RLC4_MIDCMD_DATA0 ++#define SDMA1_RLC4_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA1_RLC4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_MIDCMD_DATA1 ++#define SDMA1_RLC4_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA1_RLC4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_MIDCMD_DATA2 ++#define SDMA1_RLC4_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA1_RLC4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_MIDCMD_DATA3 ++#define SDMA1_RLC4_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA1_RLC4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_MIDCMD_DATA4 ++#define SDMA1_RLC4_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA1_RLC4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_MIDCMD_DATA5 ++#define SDMA1_RLC4_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA1_RLC4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_MIDCMD_DATA6 ++#define SDMA1_RLC4_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA1_RLC4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_MIDCMD_DATA7 ++#define SDMA1_RLC4_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA1_RLC4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_MIDCMD_DATA8 ++#define SDMA1_RLC4_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA1_RLC4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA1_RLC4_MIDCMD_CNTL ++#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA1_RLC4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA1_RLC4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA1_RLC4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA1_RLC4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA1_RLC5_RB_CNTL ++#define SDMA1_RLC5_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC5_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA1_RLC5_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA1_RLC5_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA1_RLC5_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC5_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA1_RLC5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA1_RLC5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA1_RLC5_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA1_RLC5_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA1_RLC5_RB_BASE ++#define SDMA1_RLC5_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA1_RLC5_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_RB_BASE_HI ++#define SDMA1_RLC5_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA1_RLC5_RB_RPTR ++#define SDMA1_RLC5_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_RB_RPTR_HI ++#define SDMA1_RLC5_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_RB_WPTR ++#define SDMA1_RLC5_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_RB_WPTR_HI ++#define SDMA1_RLC5_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_RB_WPTR_POLL_CNTL ++#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA1_RLC5_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA1_RLC5_RB_RPTR_ADDR_HI ++#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_RB_RPTR_ADDR_LO ++#define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC5_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA1_RLC5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC5_IB_CNTL ++#define SDMA1_RLC5_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA1_RLC5_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA1_RLC5_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA1_RLC5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA1_RLC5_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA1_RLC5_IB_RPTR ++#define SDMA1_RLC5_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC5_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC5_IB_OFFSET ++#define SDMA1_RLC5_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC5_IB_BASE_LO ++#define SDMA1_RLC5_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA1_RLC5_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA1_RLC5_IB_BASE_HI ++#define SDMA1_RLC5_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_IB_SIZE ++#define SDMA1_RLC5_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA1_RLC5_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC5_SKIP_CNTL ++#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA1_RLC5_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA1_RLC5_CONTEXT_STATUS ++#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA1_RLC5_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA1_RLC5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA1_RLC5_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA1_RLC5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA1_RLC5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA1_RLC5_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA1_RLC5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA1_RLC5_DOORBELL ++#define SDMA1_RLC5_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA1_RLC5_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA1_RLC5_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA1_RLC5_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA1_RLC5_STATUS ++#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA1_RLC5_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA1_RLC5_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA1_RLC5_DOORBELL_LOG ++#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA1_RLC5_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA1_RLC5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA1_RLC5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA1_RLC5_WATERMARK ++#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA1_RLC5_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA1_RLC5_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA1_RLC5_DOORBELL_OFFSET ++#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA1_RLC5_CSA_ADDR_LO ++#define SDMA1_RLC5_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC5_CSA_ADDR_HI ++#define SDMA1_RLC5_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_IB_SUB_REMAIN ++#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA1_RLC5_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC5_PREEMPT ++#define SDMA1_RLC5_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA1_RLC5_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA1_RLC5_DUMMY_REG ++#define SDMA1_RLC5_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA1_RLC5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI ++#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO ++#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC5_RB_AQL_CNTL ++#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA1_RLC5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA1_RLC5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA1_RLC5_MINOR_PTR_UPDATE ++#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA1_RLC5_MIDCMD_DATA0 ++#define SDMA1_RLC5_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA1_RLC5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_MIDCMD_DATA1 ++#define SDMA1_RLC5_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA1_RLC5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_MIDCMD_DATA2 ++#define SDMA1_RLC5_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA1_RLC5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_MIDCMD_DATA3 ++#define SDMA1_RLC5_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA1_RLC5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_MIDCMD_DATA4 ++#define SDMA1_RLC5_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA1_RLC5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_MIDCMD_DATA5 ++#define SDMA1_RLC5_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA1_RLC5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_MIDCMD_DATA6 ++#define SDMA1_RLC5_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA1_RLC5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_MIDCMD_DATA7 ++#define SDMA1_RLC5_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA1_RLC5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_MIDCMD_DATA8 ++#define SDMA1_RLC5_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA1_RLC5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA1_RLC5_MIDCMD_CNTL ++#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA1_RLC5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA1_RLC5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA1_RLC5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA1_RLC5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA1_RLC6_RB_CNTL ++#define SDMA1_RLC6_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC6_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA1_RLC6_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA1_RLC6_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA1_RLC6_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC6_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA1_RLC6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA1_RLC6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA1_RLC6_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA1_RLC6_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA1_RLC6_RB_BASE ++#define SDMA1_RLC6_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA1_RLC6_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_RB_BASE_HI ++#define SDMA1_RLC6_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA1_RLC6_RB_RPTR ++#define SDMA1_RLC6_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_RB_RPTR_HI ++#define SDMA1_RLC6_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_RB_WPTR ++#define SDMA1_RLC6_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_RB_WPTR_HI ++#define SDMA1_RLC6_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_RB_WPTR_POLL_CNTL ++#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA1_RLC6_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA1_RLC6_RB_RPTR_ADDR_HI ++#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_RB_RPTR_ADDR_LO ++#define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC6_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA1_RLC6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC6_IB_CNTL ++#define SDMA1_RLC6_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA1_RLC6_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA1_RLC6_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA1_RLC6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA1_RLC6_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA1_RLC6_IB_RPTR ++#define SDMA1_RLC6_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC6_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC6_IB_OFFSET ++#define SDMA1_RLC6_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC6_IB_BASE_LO ++#define SDMA1_RLC6_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA1_RLC6_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA1_RLC6_IB_BASE_HI ++#define SDMA1_RLC6_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_IB_SIZE ++#define SDMA1_RLC6_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA1_RLC6_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC6_SKIP_CNTL ++#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA1_RLC6_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA1_RLC6_CONTEXT_STATUS ++#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA1_RLC6_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA1_RLC6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA1_RLC6_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA1_RLC6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA1_RLC6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA1_RLC6_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA1_RLC6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA1_RLC6_DOORBELL ++#define SDMA1_RLC6_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA1_RLC6_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA1_RLC6_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA1_RLC6_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA1_RLC6_STATUS ++#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA1_RLC6_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA1_RLC6_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA1_RLC6_DOORBELL_LOG ++#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA1_RLC6_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA1_RLC6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA1_RLC6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA1_RLC6_WATERMARK ++#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA1_RLC6_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA1_RLC6_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA1_RLC6_DOORBELL_OFFSET ++#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA1_RLC6_CSA_ADDR_LO ++#define SDMA1_RLC6_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC6_CSA_ADDR_HI ++#define SDMA1_RLC6_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_IB_SUB_REMAIN ++#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA1_RLC6_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC6_PREEMPT ++#define SDMA1_RLC6_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA1_RLC6_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA1_RLC6_DUMMY_REG ++#define SDMA1_RLC6_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA1_RLC6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI ++#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO ++#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC6_RB_AQL_CNTL ++#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA1_RLC6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA1_RLC6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA1_RLC6_MINOR_PTR_UPDATE ++#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA1_RLC6_MIDCMD_DATA0 ++#define SDMA1_RLC6_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA1_RLC6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_MIDCMD_DATA1 ++#define SDMA1_RLC6_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA1_RLC6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_MIDCMD_DATA2 ++#define SDMA1_RLC6_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA1_RLC6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_MIDCMD_DATA3 ++#define SDMA1_RLC6_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA1_RLC6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_MIDCMD_DATA4 ++#define SDMA1_RLC6_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA1_RLC6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_MIDCMD_DATA5 ++#define SDMA1_RLC6_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA1_RLC6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_MIDCMD_DATA6 ++#define SDMA1_RLC6_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA1_RLC6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_MIDCMD_DATA7 ++#define SDMA1_RLC6_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA1_RLC6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_MIDCMD_DATA8 ++#define SDMA1_RLC6_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA1_RLC6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA1_RLC6_MIDCMD_CNTL ++#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA1_RLC6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA1_RLC6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA1_RLC6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA1_RLC6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++//SDMA1_RLC7_RB_CNTL ++#define SDMA1_RLC7_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC7_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 ++#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc ++#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd ++#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 ++#define SDMA1_RLC7_RB_CNTL__RB_PRIV__SHIFT 0x17 ++#define SDMA1_RLC7_RB_CNTL__RB_VMID__SHIFT 0x18 ++#define SDMA1_RLC7_RB_CNTL__RB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC7_RB_CNTL__RB_SIZE_MASK 0x0000003EL ++#define SDMA1_RLC7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L ++#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L ++#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L ++#define SDMA1_RLC7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L ++#define SDMA1_RLC7_RB_CNTL__RB_PRIV_MASK 0x00800000L ++#define SDMA1_RLC7_RB_CNTL__RB_VMID_MASK 0x0F000000L ++//SDMA1_RLC7_RB_BASE ++#define SDMA1_RLC7_RB_BASE__ADDR__SHIFT 0x0 ++#define SDMA1_RLC7_RB_BASE__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_RB_BASE_HI ++#define SDMA1_RLC7_RB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL ++//SDMA1_RLC7_RB_RPTR ++#define SDMA1_RLC7_RB_RPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_RB_RPTR_HI ++#define SDMA1_RLC7_RB_RPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_RB_WPTR ++#define SDMA1_RLC7_RB_WPTR__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_RB_WPTR_HI ++#define SDMA1_RLC7_RB_WPTR_HI__OFFSET__SHIFT 0x0 ++#define SDMA1_RLC7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_RB_WPTR_POLL_CNTL ++#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 ++#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 ++#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 ++#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 ++#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L ++#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L ++#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L ++#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L ++#define SDMA1_RLC7_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L ++//SDMA1_RLC7_RB_RPTR_ADDR_HI ++#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_RB_RPTR_ADDR_LO ++#define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE__SHIFT 0x0 ++#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC7_RB_RPTR_ADDR_LO__RPTR_WB_IDLE_MASK 0x00000001L ++#define SDMA1_RLC7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC7_IB_CNTL ++#define SDMA1_RLC7_IB_CNTL__IB_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 ++#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 ++#define SDMA1_RLC7_IB_CNTL__CMD_VMID__SHIFT 0x10 ++#define SDMA1_RLC7_IB_CNTL__IB_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L ++#define SDMA1_RLC7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L ++#define SDMA1_RLC7_IB_CNTL__CMD_VMID_MASK 0x000F0000L ++//SDMA1_RLC7_IB_RPTR ++#define SDMA1_RLC7_IB_RPTR__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC7_IB_RPTR__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC7_IB_OFFSET ++#define SDMA1_RLC7_IB_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL ++//SDMA1_RLC7_IB_BASE_LO ++#define SDMA1_RLC7_IB_BASE_LO__ADDR__SHIFT 0x5 ++#define SDMA1_RLC7_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L ++//SDMA1_RLC7_IB_BASE_HI ++#define SDMA1_RLC7_IB_BASE_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_IB_SIZE ++#define SDMA1_RLC7_IB_SIZE__SIZE__SHIFT 0x0 ++#define SDMA1_RLC7_IB_SIZE__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC7_SKIP_CNTL ++#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 ++#define SDMA1_RLC7_SKIP_CNTL__SKIP_COUNT_MASK 0x000FFFFFL ++//SDMA1_RLC7_CONTEXT_STATUS ++#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 ++#define SDMA1_RLC7_CONTEXT_STATUS__IDLE__SHIFT 0x2 ++#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 ++#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 ++#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 ++#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 ++#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 ++#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa ++#define SDMA1_RLC7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L ++#define SDMA1_RLC7_CONTEXT_STATUS__IDLE_MASK 0x00000004L ++#define SDMA1_RLC7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L ++#define SDMA1_RLC7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L ++#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L ++#define SDMA1_RLC7_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L ++#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L ++#define SDMA1_RLC7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L ++//SDMA1_RLC7_DOORBELL ++#define SDMA1_RLC7_DOORBELL__ENABLE__SHIFT 0x1c ++#define SDMA1_RLC7_DOORBELL__CAPTURED__SHIFT 0x1e ++#define SDMA1_RLC7_DOORBELL__ENABLE_MASK 0x10000000L ++#define SDMA1_RLC7_DOORBELL__CAPTURED_MASK 0x40000000L ++//SDMA1_RLC7_STATUS ++#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 ++#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 ++#define SDMA1_RLC7_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL ++#define SDMA1_RLC7_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L ++//SDMA1_RLC7_DOORBELL_LOG ++#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 ++#define SDMA1_RLC7_DOORBELL_LOG__DATA__SHIFT 0x2 ++#define SDMA1_RLC7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L ++#define SDMA1_RLC7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL ++//SDMA1_RLC7_WATERMARK ++#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 ++#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 ++#define SDMA1_RLC7_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL ++#define SDMA1_RLC7_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L ++//SDMA1_RLC7_DOORBELL_OFFSET ++#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 ++#define SDMA1_RLC7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL ++//SDMA1_RLC7_CSA_ADDR_LO ++#define SDMA1_RLC7_CSA_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC7_CSA_ADDR_HI ++#define SDMA1_RLC7_CSA_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_IB_SUB_REMAIN ++#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 ++#define SDMA1_RLC7_IB_SUB_REMAIN__SIZE_MASK 0x000FFFFFL ++//SDMA1_RLC7_PREEMPT ++#define SDMA1_RLC7_PREEMPT__IB_PREEMPT__SHIFT 0x0 ++#define SDMA1_RLC7_PREEMPT__IB_PREEMPT_MASK 0x00000001L ++//SDMA1_RLC7_DUMMY_REG ++#define SDMA1_RLC7_DUMMY_REG__DUMMY__SHIFT 0x0 ++#define SDMA1_RLC7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI ++#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 ++#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO ++#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 ++#define SDMA1_RLC7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL ++//SDMA1_RLC7_RB_AQL_CNTL ++#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 ++#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 ++#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 ++#define SDMA1_RLC7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L ++#define SDMA1_RLC7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL ++#define SDMA1_RLC7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L ++//SDMA1_RLC7_MINOR_PTR_UPDATE ++#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 ++#define SDMA1_RLC7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L ++//SDMA1_RLC7_MIDCMD_DATA0 ++#define SDMA1_RLC7_MIDCMD_DATA0__DATA0__SHIFT 0x0 ++#define SDMA1_RLC7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_MIDCMD_DATA1 ++#define SDMA1_RLC7_MIDCMD_DATA1__DATA1__SHIFT 0x0 ++#define SDMA1_RLC7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_MIDCMD_DATA2 ++#define SDMA1_RLC7_MIDCMD_DATA2__DATA2__SHIFT 0x0 ++#define SDMA1_RLC7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_MIDCMD_DATA3 ++#define SDMA1_RLC7_MIDCMD_DATA3__DATA3__SHIFT 0x0 ++#define SDMA1_RLC7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_MIDCMD_DATA4 ++#define SDMA1_RLC7_MIDCMD_DATA4__DATA4__SHIFT 0x0 ++#define SDMA1_RLC7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_MIDCMD_DATA5 ++#define SDMA1_RLC7_MIDCMD_DATA5__DATA5__SHIFT 0x0 ++#define SDMA1_RLC7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_MIDCMD_DATA6 ++#define SDMA1_RLC7_MIDCMD_DATA6__DATA6__SHIFT 0x0 ++#define SDMA1_RLC7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_MIDCMD_DATA7 ++#define SDMA1_RLC7_MIDCMD_DATA7__DATA7__SHIFT 0x0 ++#define SDMA1_RLC7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_MIDCMD_DATA8 ++#define SDMA1_RLC7_MIDCMD_DATA8__DATA8__SHIFT 0x0 ++#define SDMA1_RLC7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL ++//SDMA1_RLC7_MIDCMD_CNTL ++#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 ++#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 ++#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 ++#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 ++#define SDMA1_RLC7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L ++#define SDMA1_RLC7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L ++#define SDMA1_RLC7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L ++#define SDMA1_RLC7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L ++ ++#endif +-- +2.17.1 + |