diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5560-drm-amdgpu-vcn-Remove-DPG-mode-unused-steps-during-v.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/5560-drm-amdgpu-vcn-Remove-DPG-mode-unused-steps-during-v.patch | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5560-drm-amdgpu-vcn-Remove-DPG-mode-unused-steps-during-v.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5560-drm-amdgpu-vcn-Remove-DPG-mode-unused-steps-during-v.patch new file mode 100644 index 00000000..39a79a8f --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5560-drm-amdgpu-vcn-Remove-DPG-mode-unused-steps-during-v.patch @@ -0,0 +1,78 @@ +From 1afaff692799e1bdc080b413fec9d9076499745b Mon Sep 17 00:00:00 2001 +From: James Zhu <James.Zhu@amd.com> +Date: Thu, 4 Oct 2018 16:09:33 -0400 +Subject: [PATCH 5560/5725] drm/amdgpu/vcn:Remove DPG mode unused steps during + vcn start + +Remove Dynamic Power Gate mode unused steps during VCN start + +Signed-off-by: James Zhu <James.Zhu@amd.com> +Acked-by: Leo Liu <leo.liu@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 28 +--------------------------- + 1 file changed, 1 insertion(+), 27 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +index 86bb57c..bc58658 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -981,22 +981,6 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, + 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); + +- /* stall UMC and register bus before resetting VCPU */ +- WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, +- UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); +- +- /* put LMI, VCPU, RBC etc... into reset */ +- WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, +- UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | +- UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | +- UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | +- UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | +- UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | +- UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | +- UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | +- UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, +- 0xFFFFFFFF, 0); +- + /* initialize VCN memory controller */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, + (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | +@@ -1039,14 +1023,6 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); + +- /* take all subblocks out of reset, except VCPU */ +- WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, +- UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 0xFFFFFFFF, 0); +- +- /* enable VCPU clock */ +- WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, +- UVD_VCPU_CNTL__CLK_EN_MASK, 0xFFFFFFFF, 0); +- + /* enable UMC */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, + 0, UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0); +@@ -1056,8 +1032,7 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) + + /* enable master interrupt */ + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, +- (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), +- (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK), 0); ++ UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); + + vcn_v1_0_clock_gating_dpg_mode(adev, 1); + /* setup mmUVD_LMI_CTRL */ +@@ -1085,7 +1060,6 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) + tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); +- tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); + tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); + WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); +-- +2.7.4 + |