diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5553-drm-amdgpu-vcn-Update-latest-UVD_MPC-register-for-VC.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/5553-drm-amdgpu-vcn-Update-latest-UVD_MPC-register-for-VC.patch | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5553-drm-amdgpu-vcn-Update-latest-UVD_MPC-register-for-VC.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5553-drm-amdgpu-vcn-Update-latest-UVD_MPC-register-for-VC.patch new file mode 100644 index 00000000..39f59202 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5553-drm-amdgpu-vcn-Update-latest-UVD_MPC-register-for-VC.patch @@ -0,0 +1,89 @@ +From d4b9bec1d6b4c89cd1b220849de0dde8795aad51 Mon Sep 17 00:00:00 2001 +From: James Zhu <James.Zhu@amd.com> +Date: Tue, 2 Oct 2018 14:55:46 -0400 +Subject: [PATCH 5553/5725] drm/amdgpu/vcn:Update latest UVD_MPC register for + VCN + +Update latest UVD_MPC register for VCN. Use defined +macro to replace value for readability. + +Signed-off-by: James Zhu <James.Zhu@amd.com> +Acked-by: Leo Liu <leo.liu@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 52 +++++++++++++++++++++++++++-------- + 1 file changed, 40 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +index 9cf544d..6796a82 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -785,12 +785,27 @@ static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) + #endif + WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); + +- WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040); +- WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0); +- WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040); +- WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0); +- WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_ALU, 0); +- WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 0x88); ++ tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); ++ tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; ++ tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; ++ WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); ++ ++ WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, ++ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | ++ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | ++ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | ++ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); ++ ++ WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, ++ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | ++ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | ++ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | ++ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); ++ ++ WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, ++ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | ++ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | ++ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); + + /* take all subblocks out of reset, except VCPU */ + WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, +@@ -981,12 +996,25 @@ static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) + #endif + WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); + +- WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, 0x40c2040, 0xFFFFFFFF, 0); +- WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA1, 0x0, 0xFFFFFFFF, 0); +- WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, 0x40c2040, 0xFFFFFFFF, 0); +- WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB1, 0x0, 0xFFFFFFFF, 0); +- WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_ALU, 0, 0xFFFFFFFF, 0); +- WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, 0x88, 0xFFFFFFFF, 0); ++ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL, ++ 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0); ++ ++ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, ++ ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | ++ (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | ++ (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | ++ (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); ++ ++ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, ++ ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | ++ (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | ++ (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | ++ (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); ++ ++ WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, ++ ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | ++ (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | ++ (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); + + vcn_v1_0_mc_resume_dpg_mode(adev); + +-- +2.7.4 + |