diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5552-drm-amdgpu-vcn-Add-new-register-offset-mask-for-VCN.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/5552-drm-amdgpu-vcn-Add-new-register-offset-mask-for-VCN.patch | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5552-drm-amdgpu-vcn-Add-new-register-offset-mask-for-VCN.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5552-drm-amdgpu-vcn-Add-new-register-offset-mask-for-VCN.patch new file mode 100644 index 00000000..5a8e8d1d --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5552-drm-amdgpu-vcn-Add-new-register-offset-mask-for-VCN.patch @@ -0,0 +1,101 @@ +From 75272cc31f41c912385622cfc5fcf1b9765252fb Mon Sep 17 00:00:00 2001 +From: James Zhu <James.Zhu@amd.com> +Date: Tue, 2 Oct 2018 14:38:18 -0400 +Subject: [PATCH 5552/5725] drm/amdgpu/vcn:Add new register offset/mask for VCN + +Add new register offset/mask for VCN to support +latest VCN implementation. + +Signed-off-by: James Zhu <James.Zhu@amd.com> +Acked-by: Leo Liu <leo.liu@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 14 ++++++++++++++ + .../gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h | 18 ++++++++++++++++++ + 2 files changed, 32 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h +index 4b7da58..442ca7c 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h +@@ -82,6 +82,18 @@ + #define mmUVD_LCM_CGC_CNTRL 0x0123 + #define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1 + ++#define mmUVD_MIF_CURR_UV_ADDR_CONFIG 0x0184 ++#define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX 1 ++#define mmUVD_MIF_REF_UV_ADDR_CONFIG 0x0185 ++#define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX 1 ++#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG 0x0186 ++#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX 1 ++#define mmUVD_MIF_CURR_ADDR_CONFIG 0x0192 ++#define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX 1 ++#define mmUVD_MIF_REF_ADDR_CONFIG 0x0193 ++#define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX 1 ++#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x01c5 ++#define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX 1 + + // addressBlock: uvd_uvdnpdec + // base address: 0x20000 +@@ -327,6 +339,8 @@ + #define mmUVD_LMI_VM_CTRL_BASE_IDX 1 + #define mmUVD_LMI_SWAP_CNTL 0x056d + #define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1 ++#define mmUVD_MPC_CNTL 0x0577 ++#define mmUVD_MPC_CNTL_BASE_IDX 1 + #define mmUVD_MPC_SET_MUXA0 0x0579 + #define mmUVD_MPC_SET_MUXA0_BASE_IDX 1 + #define mmUVD_MPC_SET_MUXA1 0x057a +diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h +index 26382f5..63457f9 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h +@@ -985,6 +985,7 @@ + #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 + #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 + #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb ++#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 + #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L + #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L + #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L +@@ -993,6 +994,7 @@ + #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L + #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L + #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L ++#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L + //UVD_MASTINT_EN + #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 + #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 +@@ -1045,6 +1047,19 @@ + #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L + #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L + #define UVD_LMI_CTRL__RFU_MASK 0xF8000000L ++//UVD_LMI_STATUS ++#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 ++#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 ++#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 ++#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 ++#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 ++#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 ++#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L ++#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L ++#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L ++#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L ++#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L ++#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L + //UVD_LMI_SWAP_CNTL + #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 + #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 +@@ -1078,6 +1093,9 @@ + #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L + #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L + #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L ++//UVD_MPC_CNTL ++#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 ++#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L + //UVD_MPC_SET_MUXA0 + #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 + #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 +-- +2.7.4 + |