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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5425-drm-amd-display-Refactor-FPGA-specific-link-setup.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/5425-drm-amd-display-Refactor-FPGA-specific-link-setup.patch147
1 files changed, 147 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5425-drm-amd-display-Refactor-FPGA-specific-link-setup.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5425-drm-amd-display-Refactor-FPGA-specific-link-setup.patch
new file mode 100644
index 00000000..5756cbe9
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5425-drm-amd-display-Refactor-FPGA-specific-link-setup.patch
@@ -0,0 +1,147 @@
+From 1b5099a67b966ce7d2a8bf4562409e5bc19e48a2 Mon Sep 17 00:00:00 2001
+From: Nikola Cornij <nikola.cornij@amd.com>
+Date: Thu, 16 Aug 2018 14:27:11 -0400
+Subject: [PATCH 5425/5725] drm/amd/display: Refactor FPGA-specific link setup
+
+FPGA doesn't program backend, so we don't need certain link settings
+(audio stream for example).
+
+Change-Id: I12ebdbefb23a0c53a6c7edc749a5e47fbdbf68a6
+Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 56 ++++++++++++----------
+ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 15 +-----
+ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 +
+ 3 files changed, 32 insertions(+), 40 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+index 2dfdcc9..bad65c8 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+@@ -2559,23 +2559,24 @@ void core_link_enable_stream(
+ pipe_ctx->stream_res.stream_enc,
+ &stream->timing);
+
+- resource_build_info_frame(pipe_ctx);
+- core_dc->hwss.update_info_frame(pipe_ctx);
+-
+- /* eDP lit up by bios already, no need to enable again. */
+- if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
+- pipe_ctx->stream->apply_edp_fast_boot_optimization) {
+- pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
+- pipe_ctx->stream->dpms_off = false;
+- return;
+- }
++ if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
++ resource_build_info_frame(pipe_ctx);
++ core_dc->hwss.update_info_frame(pipe_ctx);
++
++ /* eDP lit up by bios already, no need to enable again. */
++ if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
++ pipe_ctx->stream->apply_edp_fast_boot_optimization) {
++ pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
++ pipe_ctx->stream->dpms_off = false;
++ return;
++ }
+
+- if (pipe_ctx->stream->dpms_off)
+- return;
++ if (pipe_ctx->stream->dpms_off)
++ return;
+
+- status = enable_link(state, pipe_ctx);
++ status = enable_link(state, pipe_ctx);
+
+- if (status != DC_OK) {
++ if (status != DC_OK) {
+ DC_LOG_WARNING("enabling link %u failed: %d\n",
+ pipe_ctx->stream->sink->link->link_index,
+ status);
+@@ -2590,23 +2591,26 @@ void core_link_enable_stream(
+ BREAK_TO_DEBUGGER();
+ return;
+ }
+- }
++ }
+
+- core_dc->hwss.enable_audio_stream(pipe_ctx);
++ core_dc->hwss.enable_audio_stream(pipe_ctx);
+
+- /* turn off otg test pattern if enable */
+- if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
+- pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
+- CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+- COLOR_DEPTH_UNDEFINED);
++ /* turn off otg test pattern if enable */
++ if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
++ pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
++ CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
++ COLOR_DEPTH_UNDEFINED);
+
+- core_dc->hwss.enable_stream(pipe_ctx);
++ core_dc->hwss.enable_stream(pipe_ctx);
+
+- if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
+- allocate_mst_payload(pipe_ctx);
++ if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
++ allocate_mst_payload(pipe_ctx);
++
++ core_dc->hwss.unblank_stream(pipe_ctx,
++ &pipe_ctx->stream->sink->link->cur_link_settings);
++
++ }
+
+- core_dc->hwss.unblank_stream(pipe_ctx,
+- &pipe_ctx->stream->sink->link->cur_link_settings);
+ }
+
+ void core_link_disable_stream(struct pipe_ctx *pipe_ctx, int option)
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index d1add1b..2d7d13b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -1377,26 +1377,13 @@ static enum dc_status apply_single_controller_ctx_to_hw(
+ /* */
+ dc->hwss.enable_stream_timing(pipe_ctx, context, dc);
+
+- /* FPGA does not program backend */
+- if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
+- pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
+- pipe_ctx->stream_res.opp,
+- COLOR_SPACE_YCBCR601,
+- stream->timing.display_color_depth,
+- pipe_ctx->stream->signal);
+-
+- pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
+- pipe_ctx->stream_res.opp,
+- &stream->bit_depth_params,
+- &stream->clamping);
+- return DC_OK;
+- }
+ /* TODO: move to stream encoder */
+ if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
+ if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
+ BREAK_TO_DEBUGGER();
+ return DC_ERROR_UNEXPECTED;
+ }
++
+ pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
+ pipe_ctx->stream_res.opp,
+ COLOR_SPACE_YCBCR601,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 6bd4ec3..a881ff5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -44,6 +44,7 @@
+ #include "dcn10_hubp.h"
+ #include "dcn10_hubbub.h"
+ #include "dcn10_cm_common.h"
++#include "dc_link_dp.h"
+
+ #define DC_LOGGER_INIT(logger)
+
+--
+2.7.4
+