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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5133-drm-amd-powerplay-add-vega20-pre_display_config_chan.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/5133-drm-amd-powerplay-add-vega20-pre_display_config_chan.patch83
1 files changed, 83 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5133-drm-amd-powerplay-add-vega20-pre_display_config_chan.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5133-drm-amd-powerplay-add-vega20-pre_display_config_chan.patch
new file mode 100644
index 00000000..df45e4f6
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5133-drm-amd-powerplay-add-vega20-pre_display_config_chan.patch
@@ -0,0 +1,83 @@
+From a14d285dd750ef6d28da806486d31454e089c14e Mon Sep 17 00:00:00 2001
+From: Evan Quan <evan.quan@amd.com>
+Date: Wed, 9 May 2018 11:14:06 +0800
+Subject: [PATCH 5133/5725] drm/amd/powerplay: add vega20
+ pre_display_config_changed callback
+
+fix possible handshake hang and video playback crash
+
+Corner cases:
+ - Handshake between SMU and DCE causes hangs when CRTC is not
+ enabled
+ - System crash occurs when starting 4K playback with Movies and TV
+ in an SLS configuration
+
+Signed-off-by: Evan Quan <evan.quan@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 41 ++++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+index 7b6e48a..5b0c654 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+@@ -1874,6 +1874,45 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
+ return size;
+ }
+
++static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
++ struct vega20_single_dpm_table *dpm_table)
++{
++ struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
++ int ret = 0;
++
++ if (data->smu_features[GNLD_DPM_UCLK].enabled) {
++ PP_ASSERT_WITH_CODE(dpm_table->count > 0,
++ "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
++ return -EINVAL);
++ PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
++ "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
++ return -EINVAL);
++
++ dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
++ PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
++ PPSMC_MSG_SetHardMinByFreq,
++ (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level)),
++ "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
++ return ret);
++ }
++
++ return ret;
++}
++
++static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
++{
++ struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
++ int ret = 0;
++
++ smum_send_msg_to_smc_with_parameter(hwmgr,
++ PPSMC_MSG_NumOfDisplays, 0);
++
++ ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
++ &data->dpm_table.mem_table);
++
++ return ret;
++}
++
+ static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
+ {
+ struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
+@@ -2277,6 +2316,8 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
+ /* power state related */
+ .apply_clocks_adjust_rules =
+ vega20_apply_clocks_adjust_rules,
++ .pre_display_config_changed =
++ vega20_pre_display_configuration_changed_task,
+ .display_config_changed =
+ vega20_display_configuration_changed_task,
+ .check_smc_update_required_for_display_configuration =
+--
+2.7.4
+