diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/5114-drm-amdgpu-enable-ABGR-and-XBGR-formats-v2.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/5114-drm-amdgpu-enable-ABGR-and-XBGR-formats-v2.patch | 174 |
1 files changed, 174 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/5114-drm-amdgpu-enable-ABGR-and-XBGR-formats-v2.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/5114-drm-amdgpu-enable-ABGR-and-XBGR-formats-v2.patch new file mode 100644 index 00000000..8d8d9326 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/5114-drm-amdgpu-enable-ABGR-and-XBGR-formats-v2.patch @@ -0,0 +1,174 @@ +From f68e8cda32e5e585c1613f025e000caa21b484f7 Mon Sep 17 00:00:00 2001 +From: Mauro Rossi <issor.oruam@gmail.com> +Date: Sun, 12 Aug 2018 21:43:02 +0200 +Subject: [PATCH 5114/5725] drm/amdgpu: enable ABGR and XBGR formats (v2) + +Add support for DRM_FORMAT_{A,X}BGR8888 in amdgpu with amd dc disabled + +(v2) Crossbar registers are defined and used to swap red and blue channels, + keeping the existing coding style in each of the dce modules. + After setting crossbar bits in fb_swap, use bitwise OR for big endian + where required in DCE6 and DCE8 which do not rely on REG_SET_FIELD() + +Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 11 +++++++++++ + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 11 +++++++++++ + drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 10 ++++++++++ + drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 10 ++++++++++ + drivers/gpu/drm/amd/amdgpu/si_enums.h | 20 ++++++++++++++++++++ + drivers/gpu/drm/amd/amdgpu/sid.h | 20 ++++++++++++++++++++ + 6 files changed, 82 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +index 34cdcc8..de88444 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +@@ -1947,6 +1947,17 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, + /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ + bypass_lut = true; + break; ++ case DRM_FORMAT_XBGR8888: ++ case DRM_FORMAT_ABGR8888: ++ fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); ++ fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); ++ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2); ++ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2); ++#ifdef __BIG_ENDIAN ++ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ++ ENDIAN_8IN32); ++#endif ++ break; + default: + DRM_ERROR("Unsupported screen format %s\n", + drm_get_format_name(target_fb->format->format, &format_name)); +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +index fd3441e..d45c2d8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +@@ -1989,6 +1989,17 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, + /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ + bypass_lut = true; + break; ++ case DRM_FORMAT_XBGR8888: ++ case DRM_FORMAT_ABGR8888: ++ fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); ++ fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); ++ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2); ++ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2); ++#ifdef __BIG_ENDIAN ++ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ++ ENDIAN_8IN32); ++#endif ++ break; + default: + DRM_ERROR("Unsupported screen format %s\n", + drm_get_format_name(target_fb->format->format, &format_name)); +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +index b185bd7..3d214bd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +@@ -1892,6 +1892,16 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, + /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ + bypass_lut = true; + break; ++ case DRM_FORMAT_XBGR8888: ++ case DRM_FORMAT_ABGR8888: ++ fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | ++ GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); ++ fb_swap = (GRPH_RED_CROSSBAR(GRPH_RED_SEL_B) | ++ GRPH_BLUE_CROSSBAR(GRPH_BLUE_SEL_R)); ++#ifdef __BIG_ENDIAN ++ fb_swap |= GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); ++#endif ++ break; + default: + DRM_ERROR("Unsupported screen format %s\n", + drm_get_format_name(target_fb->format->format, &format_name)); +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +index bff4b94..4798f45 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +@@ -1869,6 +1869,16 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, + /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ + bypass_lut = true; + break; ++ case DRM_FORMAT_XBGR8888: ++ case DRM_FORMAT_ABGR8888: ++ fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | ++ (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); ++ fb_swap = ((GRPH_RED_SEL_B << GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT) | ++ (GRPH_BLUE_SEL_R << GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT)); ++#ifdef __BIG_ENDIAN ++ fb_swap |= (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); ++#endif ++ break; + default: + DRM_ERROR("Unsupported screen format %s\n", + drm_get_format_name(target_fb->format->format, &format_name)); +diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h b/drivers/gpu/drm/amd/amdgpu/si_enums.h +index dc9e0e6..790ba46 100644 +--- a/drivers/gpu/drm/amd/amdgpu/si_enums.h ++++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h +@@ -46,6 +46,26 @@ + #define GRPH_ENDIAN_8IN16 1 + #define GRPH_ENDIAN_8IN32 2 + #define GRPH_ENDIAN_8IN64 3 ++#define GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) ++#define GRPH_RED_SEL_R 0 ++#define GRPH_RED_SEL_G 1 ++#define GRPH_RED_SEL_B 2 ++#define GRPH_RED_SEL_A 3 ++#define GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) ++#define GRPH_GREEN_SEL_G 0 ++#define GRPH_GREEN_SEL_B 1 ++#define GRPH_GREEN_SEL_A 2 ++#define GRPH_GREEN_SEL_R 3 ++#define GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) ++#define GRPH_BLUE_SEL_B 0 ++#define GRPH_BLUE_SEL_A 1 ++#define GRPH_BLUE_SEL_R 2 ++#define GRPH_BLUE_SEL_G 3 ++#define GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) ++#define GRPH_ALPHA_SEL_A 0 ++#define GRPH_ALPHA_SEL_R 1 ++#define GRPH_ALPHA_SEL_G 2 ++#define GRPH_ALPHA_SEL_B 3 + + #define GRPH_DEPTH(x) (((x) & 0x3) << 0) + #define GRPH_DEPTH_8BPP 0 +diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h +index c57eff1..7cf12ad 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sid.h ++++ b/drivers/gpu/drm/amd/amdgpu/sid.h +@@ -2201,6 +2201,26 @@ + # define EVERGREEN_GRPH_ENDIAN_8IN16 1 + # define EVERGREEN_GRPH_ENDIAN_8IN32 2 + # define EVERGREEN_GRPH_ENDIAN_8IN64 3 ++#define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) ++# define EVERGREEN_GRPH_RED_SEL_R 0 ++# define EVERGREEN_GRPH_RED_SEL_G 1 ++# define EVERGREEN_GRPH_RED_SEL_B 2 ++# define EVERGREEN_GRPH_RED_SEL_A 3 ++#define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) ++# define EVERGREEN_GRPH_GREEN_SEL_G 0 ++# define EVERGREEN_GRPH_GREEN_SEL_B 1 ++# define EVERGREEN_GRPH_GREEN_SEL_A 2 ++# define EVERGREEN_GRPH_GREEN_SEL_R 3 ++#define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) ++# define EVERGREEN_GRPH_BLUE_SEL_B 0 ++# define EVERGREEN_GRPH_BLUE_SEL_A 1 ++# define EVERGREEN_GRPH_BLUE_SEL_R 2 ++# define EVERGREEN_GRPH_BLUE_SEL_G 3 ++#define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) ++# define EVERGREEN_GRPH_ALPHA_SEL_A 0 ++# define EVERGREEN_GRPH_ALPHA_SEL_R 1 ++# define EVERGREEN_GRPH_ALPHA_SEL_G 2 ++# define EVERGREEN_GRPH_ALPHA_SEL_B 3 + + #define EVERGREEN_D3VGA_CONTROL 0xf8 + #define EVERGREEN_D4VGA_CONTROL 0xf9 +-- +2.7.4 + |