diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4962-drm-amdgpu-cleanup-job-header.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4962-drm-amdgpu-cleanup-job-header.patch | 175 |
1 files changed, 175 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4962-drm-amdgpu-cleanup-job-header.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4962-drm-amdgpu-cleanup-job-header.patch new file mode 100644 index 00000000..e5dcda8e --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4962-drm-amdgpu-cleanup-job-header.patch @@ -0,0 +1,175 @@ +From a6eb67ba24df176d009277acfdb0a8ca61343edb Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Fri, 13 Jul 2018 09:50:08 +0200 +Subject: [PATCH 4962/5725] drm/amdgpu: cleanup job header +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Move job related defines, structure and function declarations to +amdgpu_job.h + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> +Acked-by: Chunming Zhou <david1.zhou@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 46 +------------------- + drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 74 +++++++++++++++++++++++++++++++++ + 2 files changed, 75 insertions(+), 45 deletions(-) + create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_job.h + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index bb1062e..d3a2e16 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -74,6 +74,7 @@ + #include "amdgpu_virt.h" + #include "amdgpu_gart.h" + #include "amdgpu_debugfs.h" ++#include "amdgpu_job.h" + + /* + * Modules parameters. +@@ -616,17 +617,6 @@ struct amdgpu_ib { + + extern const struct drm_sched_backend_ops amdgpu_sched_ops; + +-int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, +- struct amdgpu_job **job, struct amdgpu_vm *vm); +-int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, +- struct amdgpu_job **job); +- +-void amdgpu_job_free_resources(struct amdgpu_job *job); +-void amdgpu_job_free(struct amdgpu_job *job); +-int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, +- struct drm_sched_entity *entity, void *owner, +- struct dma_fence **f); +- + /* + * Queue manager + */ +@@ -1078,40 +1068,6 @@ struct amdgpu_cs_parser { + struct drm_syncobj **post_dep_syncobjs; + }; + +-#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ +-#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ +-#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ +- +-struct amdgpu_job { +- struct drm_sched_job base; +- struct amdgpu_device *adev; +- struct amdgpu_vm *vm; +- struct amdgpu_ring *ring; +- struct amdgpu_sync sync; +- struct amdgpu_sync sched_sync; +- struct amdgpu_ib *ibs; +- struct dma_fence *fence; /* the hw fence */ +- uint32_t preamble_status; +- uint32_t num_ibs; +- void *owner; +- uint64_t fence_ctx; /* the fence_context this job uses */ +- bool vm_needs_flush; +- uint64_t vm_pd_addr; +- unsigned vmid; +- unsigned pasid; +- uint32_t gds_base, gds_size; +- uint32_t gws_base, gws_size; +- uint32_t oa_base, oa_size; +- uint32_t vram_lost_counter; +- +- /* user fence handling */ +- uint64_t uf_addr; +- uint64_t uf_sequence; +- +-}; +-#define to_amdgpu_job(sched_job) \ +- container_of((sched_job), struct amdgpu_job, base) +- + static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, + uint32_t ib_idx, int idx) + { +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h +new file mode 100644 +index 0000000..35bb932 +--- /dev/null ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h +@@ -0,0 +1,74 @@ ++/* ++ * Copyright 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#ifndef __AMDGPU_JOB_H__ ++#define __AMDGPU_JOB_H__ ++ ++/* bit set means command submit involves a preamble IB */ ++#define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) ++/* bit set means preamble IB is first presented in belonging context */ ++#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) ++/* bit set means context switch occured */ ++#define AMDGPU_HAVE_CTX_SWITCH (1 << 2) ++ ++#define to_amdgpu_job(sched_job) \ ++ container_of((sched_job), struct amdgpu_job, base) ++ ++struct amdgpu_job { ++ struct drm_sched_job base; ++ struct amdgpu_device *adev; ++ struct amdgpu_vm *vm; ++ struct amdgpu_ring *ring; ++ struct amdgpu_sync sync; ++ struct amdgpu_sync sched_sync; ++ struct amdgpu_ib *ibs; ++ struct dma_fence *fence; /* the hw fence */ ++ uint32_t preamble_status; ++ uint32_t num_ibs; ++ void *owner; ++ uint64_t fence_ctx; /* the fence_context this job uses */ ++ bool vm_needs_flush; ++ uint64_t vm_pd_addr; ++ unsigned vmid; ++ unsigned pasid; ++ uint32_t gds_base, gds_size; ++ uint32_t gws_base, gws_size; ++ uint32_t oa_base, oa_size; ++ uint32_t vram_lost_counter; ++ ++ /* user fence handling */ ++ uint64_t uf_addr; ++ uint64_t uf_sequence; ++ ++}; ++ ++int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, ++ struct amdgpu_job **job, struct amdgpu_vm *vm); ++int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, ++ struct amdgpu_job **job); ++ ++void amdgpu_job_free_resources(struct amdgpu_job *job); ++void amdgpu_job_free(struct amdgpu_job *job); ++int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, ++ struct drm_sched_entity *entity, void *owner, ++ struct dma_fence **f); ++#endif +-- +2.7.4 + |