diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4955-drm-amd-display-add-HDR-visual-confirm.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4955-drm-amd-display-add-HDR-visual-confirm.patch | 205 |
1 files changed, 205 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4955-drm-amd-display-add-HDR-visual-confirm.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4955-drm-amd-display-add-HDR-visual-confirm.patch new file mode 100644 index 00000000..2b016a64 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4955-drm-amd-display-add-HDR-visual-confirm.patch @@ -0,0 +1,205 @@ +From 11f622f8b38a4bc86615f64edfe93d63631a9964 Mon Sep 17 00:00:00 2001 +From: Gloria Li <geling.li@amd.com> +Date: Tue, 3 Jul 2018 14:39:22 -0400 +Subject: [PATCH 4955/5725] drm/amd/display: add HDR visual confirm + +[Why] +Testing team wants a way to tell if HDR is on or not + +[How] +Program the overscan color to visually indicate the HDR state of the top-most plane + +Signed-off-by: Gloria Li <geling.li@amd.com> +Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> +Acked-by: Leo Li <sunpeng.li@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dc.h | 11 ++++- + drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 2 +- + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- + .../drm/amd/display/dc/dce110/dce110_transform_v.c | 2 +- + .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 7 ++- + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 50 ++++++++++++++++++++-- + 6 files changed, 63 insertions(+), 11 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index fc1aa32..966e9b9 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -170,6 +170,12 @@ struct dc_config { + bool disable_disp_pll_sharing; + }; + ++enum visual_confirm { ++ VISUAL_CONFIRM_DISABLE = 0, ++ VISUAL_CONFIRM_SURFACE = 1, ++ VISUAL_CONFIRM_HDR = 2, ++}; ++ + enum dcc_option { + DCC_ENABLE = 0, + DCC_DISABLE = 1, +@@ -203,7 +209,7 @@ struct dc_clocks { + }; + + struct dc_debug { +- bool surface_visual_confirm; ++ enum visual_confirm visual_confirm; + bool sanity_checks; + bool max_disp_clk; + bool surface_trace; +@@ -388,7 +394,8 @@ enum dc_transfer_func_predefined { + TRANSFER_FUNCTION_LINEAR, + TRANSFER_FUNCTION_UNITY, + TRANSFER_FUNCTION_HLG, +- TRANSFER_FUNCTION_HLG12 ++ TRANSFER_FUNCTION_HLG12, ++ TRANSFER_FUNCTION_GAMMA22 + }; + + struct dc_transfer_func { +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +index a02e719..ab63d0d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +@@ -155,7 +155,7 @@ static void program_overscan( + int overscan_bottom = data->v_active + - data->recout.y - data->recout.height; + +- if (xfm_dce->base.ctx->dc->debug.surface_visual_confirm) { ++ if (xfm_dce->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { + overscan_bottom += 2; + overscan_right += 2; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 8068074..8b7606e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -1256,7 +1256,7 @@ static void program_scaler(const struct dc *dc, + return; + #endif + +- if (dc->debug.surface_visual_confirm) ++ if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) + get_surface_visual_confirm_color(pipe_ctx, &color); + else + color_space_to_black_color(dc, +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c +index a7dce06..aa8d6b1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.c +@@ -235,7 +235,7 @@ static void program_overscan( + int overscan_right = data->h_active - data->recout.x - data->recout.width; + int overscan_bottom = data->v_active - data->recout.y - data->recout.height; + +- if (xfm_dce->base.ctx->dc->debug.surface_visual_confirm) { ++ if (xfm_dce->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) { + overscan_bottom += 2; + overscan_right += 2; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +index f0cc975..4a863a5d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c +@@ -621,6 +621,10 @@ static void dpp1_dscl_set_manual_ratio_init( + static void dpp1_dscl_set_recout( + struct dcn10_dpp *dpp, const struct rect *recout) + { ++ int visual_confirm_on = 0; ++ if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) ++ visual_confirm_on = 1; ++ + REG_SET_2(RECOUT_START, 0, + /* First pixel of RECOUT */ + RECOUT_START_X, recout->x, +@@ -632,8 +636,7 @@ static void dpp1_dscl_set_recout( + RECOUT_WIDTH, recout->width, + /* Number of RECOUT vertical lines */ + RECOUT_HEIGHT, recout->height +- - dpp->base.ctx->dc->debug.surface_visual_confirm * 4 * +- (dpp->base.inst + 1)); ++ - visual_confirm_on * 4 * (dpp->base.inst + 1)); + } + + /* Main function to program scaler and line buffer in manual scaling mode */ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 4795974..689aebf 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -1783,6 +1783,43 @@ static void dcn10_get_surface_visual_confirm_color( + } + } + ++static void dcn10_get_hdr_visual_confirm_color( ++ struct pipe_ctx *pipe_ctx, ++ struct tg_color *color) ++{ ++ uint32_t color_value = MAX_TG_COLOR_VALUE; ++ ++ // Determine the overscan color based on the top-most (desktop) plane's context ++ struct pipe_ctx *top_pipe_ctx = pipe_ctx; ++ ++ while (top_pipe_ctx->top_pipe != NULL) ++ top_pipe_ctx = top_pipe_ctx->top_pipe; ++ ++ switch (top_pipe_ctx->plane_res.scl_data.format) { ++ case PIXEL_FORMAT_ARGB2101010: ++ if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_UNITY) { ++ /* HDR10, ARGB2101010 - set boarder color to red */ ++ color->color_r_cr = color_value; ++ } ++ break; ++ case PIXEL_FORMAT_FP16: ++ if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) { ++ /* HDR10, FP16 - set boarder color to blue */ ++ color->color_b_cb = color_value; ++ } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) { ++ /* FreeSync 2 HDR - set boarder color to green */ ++ color->color_g_y = color_value; ++ } ++ break; ++ default: ++ /* SDR - set boarder color to Gray */ ++ color->color_r_cr = color_value/2; ++ color->color_b_cb = color_value/2; ++ color->color_g_y = color_value/2; ++ break; ++ } ++} ++ + static uint16_t fixed_point_to_int_frac( + struct fixed31_32 arg, + uint8_t integer_bits, +@@ -1877,13 +1914,17 @@ static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) + + /* TODO: proper fix once fpga works */ + +- if (dc->debug.surface_visual_confirm) ++ if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) { ++ dcn10_get_hdr_visual_confirm_color( ++ pipe_ctx, &blnd_cfg.black_color); ++ } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) { + dcn10_get_surface_visual_confirm_color( + pipe_ctx, &blnd_cfg.black_color); +- else ++ } else { + color_space_to_black_color( +- dc, pipe_ctx->stream->output_color_space, +- &blnd_cfg.black_color); ++ dc, pipe_ctx->stream->output_color_space, ++ &blnd_cfg.black_color); ++ } + + if (per_pixel_alpha) + blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA; +@@ -2163,6 +2204,7 @@ static void program_all_pipe_in_tree( + pipe_ctx->stream_res.tg); + + dc->hwss.blank_pixel_data(dc, pipe_ctx, blank); ++ + } + + if (pipe_ctx->plane_state != NULL) { +-- +2.7.4 + |