diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4949-drm-amdgpu-pp-split-out-common-smumgr-smu9-code.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4949-drm-amdgpu-pp-split-out-common-smumgr-smu9-code.patch | 920 |
1 files changed, 920 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4949-drm-amdgpu-pp-split-out-common-smumgr-smu9-code.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4949-drm-amdgpu-pp-split-out-common-smumgr-smu9-code.patch new file mode 100644 index 00000000..6481bdb9 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4949-drm-amdgpu-pp-split-out-common-smumgr-smu9-code.patch @@ -0,0 +1,920 @@ +From 8757277ccbe249636b4b0f0493a9af5c7e37b3d3 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 12 Jul 2018 14:47:30 -0500 +Subject: [PATCH 4949/5725] drm/amdgpu/pp: split out common smumgr smu9 code + +Split out the shared smumgr code for vega10 and 12 +so we don't have duplicate code for both. + +Reviewed-by: Rex Zhu <rezhu@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 44 ++--- + .../gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c | 8 +- + drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +- + drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c | 150 ++++++++++++++++ + drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h | 32 ++++ + .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 168 ++---------------- + .../gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c | 191 +++------------------ + .../gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h | 1 - + 8 files changed, 242 insertions(+), 354 deletions(-) + create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c + create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c +index c0ceb69..912d0d6 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c +@@ -477,7 +477,7 @@ static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr, + "[GetNumOfDpmLevel] failed to get dpm levels!", + return ret); + +- vega12_read_arg_from_smc(hwmgr, num_of_levels); ++ *num_of_levels = smum_get_argument(hwmgr); + PP_ASSERT_WITH_CODE(*num_of_levels > 0, + "[GetNumOfDpmLevel] number of clk levels is invalid!", + return -EINVAL); +@@ -499,11 +499,7 @@ static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr, + "[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!", + return -EINVAL); + +- result = vega12_read_arg_from_smc(hwmgr, clock); +- +- PP_ASSERT_WITH_CODE(*clock != 0, +- "[GetDPMFrequencyByIndex] Failed to get dpm frequency by index.!", +- return -EINVAL); ++ *clock = smum_get_argument(hwmgr); + + return result; + } +@@ -884,21 +880,21 @@ static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr, + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16)) == 0, + "[GetClockRanges] Failed to get max ac clock from SMC!", + return -EINVAL); +- vega12_read_arg_from_smc(hwmgr, &(clock->ACMax)); ++ clock->ACMax = smum_get_argument(hwmgr); + + /* AC Min */ + PP_ASSERT_WITH_CODE( + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16)) == 0, + "[GetClockRanges] Failed to get min ac clock from SMC!", + return -EINVAL); +- vega12_read_arg_from_smc(hwmgr, &(clock->ACMin)); ++ clock->ACMin = smum_get_argument(hwmgr); + + /* DC Max */ + PP_ASSERT_WITH_CODE( + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16)) == 0, + "[GetClockRanges] Failed to get max dc clock from SMC!", + return -EINVAL); +- vega12_read_arg_from_smc(hwmgr, &(clock->DCMax)); ++ clock->DCMax = smum_get_argument(hwmgr); + + return 0; + } +@@ -1219,7 +1215,7 @@ static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query) + "Failed to get current package power!", + return -EINVAL); + +- vega12_read_arg_from_smc(hwmgr, &value); ++ value = smum_get_argument(hwmgr); + /* power value is an integer */ + *query = value << 8; + #endif +@@ -1235,11 +1231,8 @@ static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx + PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16)) == 0, + "[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!", +- return -1); +- PP_ASSERT_WITH_CODE( +- vega12_read_arg_from_smc(hwmgr, &gfx_clk) == 0, +- "[GetCurrentGfxClkFreq] Attempt to read arg from SMC Failed", +- return -1); ++ return -EINVAL); ++ gfx_clk = smum_get_argument(hwmgr); + + *gfx_freq = gfx_clk * 100; + +@@ -1255,11 +1248,8 @@ static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_f + PP_ASSERT_WITH_CODE( + smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16)) == 0, + "[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!", +- return -1); +- PP_ASSERT_WITH_CODE( +- vega12_read_arg_from_smc(hwmgr, &mem_clk) == 0, +- "[GetCurrentMClkFreq] Attempt to read arg from SMC Failed", +- return -1); ++ return -EINVAL); ++ mem_clk = smum_get_argument(hwmgr); + + *mclk_freq = mem_clk * 100; + +@@ -1276,16 +1266,12 @@ static int vega12_get_current_activity_percent( + #if 0 + ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0); + if (!ret) { +- ret = vega12_read_arg_from_smc(hwmgr, ¤t_activity); +- if (!ret) { +- if (current_activity > 100) { +- PP_ASSERT(false, +- "[GetCurrentActivityPercent] Activity Percentage Exceeds 100!"); +- current_activity = 100; +- } +- } else ++ current_activity = smum_get_argument(hwmgr); ++ if (current_activity > 100) { + PP_ASSERT(false, +- "[GetCurrentActivityPercent] Attempt To Read Average Graphics Activity from SMU Failed!"); ++ "[GetCurrentActivityPercent] Activity Percentage Exceeds 100!"); ++ current_activity = 100; ++ } + } else + PP_ASSERT(false, + "[GetCurrentActivityPercent] Attempt To Send Get Average Graphics Activity to SMU Failed!"); +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c +index cfd9e6c..904eb2c 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c +@@ -34,11 +34,9 @@ static int vega12_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm) + PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr, + PPSMC_MSG_GetCurrentRpm), + "Attempt to get current RPM from SMC Failed!", +- return -1); +- PP_ASSERT_WITH_CODE(!vega12_read_arg_from_smc(hwmgr, +- current_rpm), +- "Attempt to read current RPM from SMC Failed!", +- return -1); ++ return -EINVAL); ++ *current_rpm = smum_get_argument(hwmgr); ++ + return 0; + } + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile +index 5e9db66..3ef862b 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile +@@ -6,7 +6,7 @@ + SMU_MGR = smumgr.o smu8_smumgr.o tonga_smumgr.o fiji_smumgr.o \ + polaris10_smumgr.o iceland_smumgr.o \ + smu7_smumgr.o vega10_smumgr.o smu10_smumgr.o ci_smumgr.o \ +- vega12_smumgr.o vegam_smumgr.o ++ vega12_smumgr.o vegam_smumgr.o smu9_smumgr.o + + AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR)) + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c +new file mode 100644 +index 0000000..aad8f07 +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c +@@ -0,0 +1,150 @@ ++/* ++ * Copyright 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++ ++#include "smumgr.h" ++#include "vega10_inc.h" ++#include "soc15_common.h" ++#include "pp_debug.h" ++ ++ ++/* MP Apertures */ ++#define MP0_Public 0x03800000 ++#define MP0_SRAM 0x03900000 ++#define MP1_Public 0x03b00000 ++#define MP1_SRAM 0x03c00004 ++ ++#define smnMP1_FIRMWARE_FLAGS 0x3010028 ++ ++bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr) ++{ ++ struct amdgpu_device *adev = hwmgr->adev; ++ uint32_t mp1_fw_flags; ++ ++ WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2, ++ (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))); ++ ++ mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2); ++ ++ if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ++ return true; ++ ++ return false; ++} ++ ++/* ++ * Check if SMC has responded to previous message. ++ * ++ * @param smumgr the address of the powerplay hardware manager. ++ * @return TRUE SMC has responded, FALSE otherwise. ++ */ ++static uint32_t smu9_wait_for_response(struct pp_hwmgr *hwmgr) ++{ ++ struct amdgpu_device *adev = hwmgr->adev; ++ uint32_t reg; ++ uint32_t ret; ++ ++ reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); ++ ++ ret = phm_wait_for_register_unequal(hwmgr, reg, ++ 0, MP1_C2PMSG_90__CONTENT_MASK); ++ ++ if (ret) ++ pr_err("No response from smu\n"); ++ ++ return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); ++} ++ ++/* ++ * Send a message to the SMC, and do not wait for its response. ++ * @param smumgr the address of the powerplay hardware manager. ++ * @param msg the message to send. ++ * @return Always return 0. ++ */ ++static int smu9_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, ++ uint16_t msg) ++{ ++ struct amdgpu_device *adev = hwmgr->adev; ++ ++ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); ++ ++ return 0; ++} ++ ++/* ++ * Send a message to the SMC, and wait for its response. ++ * @param hwmgr the address of the powerplay hardware manager. ++ * @param msg the message to send. ++ * @return Always return 0. ++ */ ++int smu9_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) ++{ ++ struct amdgpu_device *adev = hwmgr->adev; ++ uint32_t ret; ++ ++ smu9_wait_for_response(hwmgr); ++ ++ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); ++ ++ smu9_send_msg_to_smc_without_waiting(hwmgr, msg); ++ ++ ret = smu9_wait_for_response(hwmgr); ++ if (ret != 1) ++ pr_err("Failed to send message: 0x%x, ret value: 0x%x\n", msg, ret); ++ ++ return 0; ++} ++ ++/* ++ * Send a message to the SMC with parameter ++ * @param hwmgr: the address of the powerplay hardware manager. ++ * @param msg: the message to send. ++ * @param parameter: the parameter to send ++ * @return Always return 0. ++ */ ++int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, ++ uint16_t msg, uint32_t parameter) ++{ ++ struct amdgpu_device *adev = hwmgr->adev; ++ uint32_t ret; ++ ++ smu9_wait_for_response(hwmgr); ++ ++ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); ++ ++ WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); ++ ++ smu9_send_msg_to_smc_without_waiting(hwmgr, msg); ++ ++ ret = smu9_wait_for_response(hwmgr); ++ if (ret != 1) ++ pr_err("Failed message: 0x%x, input parameter: 0x%x, error code: 0x%x\n", msg, parameter, ret); ++ ++ return 0; ++} ++ ++int smu9_get_argument(struct pp_hwmgr *hwmgr) ++{ ++ struct amdgpu_device *adev = hwmgr->adev; ++ ++ return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); ++} +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h +new file mode 100644 +index 0000000..a8da281 +--- /dev/null ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h +@@ -0,0 +1,32 @@ ++/* ++ * Copyright 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#ifndef _SMU9_SMUMANAGER_H_ ++#define _SMU9_SMUMANAGER_H_ ++ ++bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr); ++int smu9_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg); ++int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, ++ uint16_t msg, uint32_t parameter); ++int smu9_get_argument(struct pp_hwmgr *hwmgr); ++ ++#endif +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c +index e84669c..5d19115 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c +@@ -28,142 +28,11 @@ + #include "vega10_hwmgr.h" + #include "vega10_ppsmc.h" + #include "smu9_driver_if.h" ++#include "smu9_smumgr.h" + #include "ppatomctrl.h" + #include "pp_debug.h" + + +-#define AVFS_EN_MSB 1568 +-#define AVFS_EN_LSB 1568 +- +-/* Microcode file is stored in this buffer */ +-#define BUFFER_SIZE 80000 +-#define MAX_STRING_SIZE 15 +-#define BUFFER_SIZETWO 131072 /* 128 *1024 */ +- +-/* MP Apertures */ +-#define MP0_Public 0x03800000 +-#define MP0_SRAM 0x03900000 +-#define MP1_Public 0x03b00000 +-#define MP1_SRAM 0x03c00004 +- +-#define smnMP1_FIRMWARE_FLAGS 0x3010028 +-#define smnMP0_FW_INTF 0x3010104 +-#define smnMP1_PUB_CTRL 0x3010b14 +- +-static bool vega10_is_smc_ram_running(struct pp_hwmgr *hwmgr) +-{ +- struct amdgpu_device *adev = hwmgr->adev; +- uint32_t mp1_fw_flags; +- +- WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2, +- (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))); +- +- mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2); +- +- if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) +- return true; +- +- return false; +-} +- +-/* +- * Check if SMC has responded to previous message. +- * +- * @param smumgr the address of the powerplay hardware manager. +- * @return TRUE SMC has responded, FALSE otherwise. +- */ +-static uint32_t vega10_wait_for_response(struct pp_hwmgr *hwmgr) +-{ +- struct amdgpu_device *adev = hwmgr->adev; +- uint32_t reg; +- uint32_t ret; +- +- reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); +- +- ret = phm_wait_for_register_unequal(hwmgr, reg, +- 0, MP1_C2PMSG_90__CONTENT_MASK); +- +- if (ret) +- pr_err("No response from smu\n"); +- +- return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); +-} +- +-/* +- * Send a message to the SMC, and do not wait for its response. +- * @param smumgr the address of the powerplay hardware manager. +- * @param msg the message to send. +- * @return Always return 0. +- */ +-static int vega10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, +- uint16_t msg) +-{ +- struct amdgpu_device *adev = hwmgr->adev; +- +- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); +- +- return 0; +-} +- +-/* +- * Send a message to the SMC, and wait for its response. +- * @param hwmgr the address of the powerplay hardware manager. +- * @param msg the message to send. +- * @return Always return 0. +- */ +-static int vega10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) +-{ +- struct amdgpu_device *adev = hwmgr->adev; +- uint32_t ret; +- +- vega10_wait_for_response(hwmgr); +- +- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); +- +- vega10_send_msg_to_smc_without_waiting(hwmgr, msg); +- +- ret = vega10_wait_for_response(hwmgr); +- if (ret != 1) +- pr_err("Failed to send message: 0x%x, ret value: 0x%x\n", msg, ret); +- +- return 0; +-} +- +-/* +- * Send a message to the SMC with parameter +- * @param hwmgr: the address of the powerplay hardware manager. +- * @param msg: the message to send. +- * @param parameter: the parameter to send +- * @return Always return 0. +- */ +-static int vega10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, +- uint16_t msg, uint32_t parameter) +-{ +- struct amdgpu_device *adev = hwmgr->adev; +- uint32_t ret; +- +- vega10_wait_for_response(hwmgr); +- +- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); +- +- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); +- +- vega10_send_msg_to_smc_without_waiting(hwmgr, msg); +- +- ret = vega10_wait_for_response(hwmgr); +- if (ret != 1) +- pr_err("Failed message: 0x%x, input parameter: 0x%x, error code: 0x%x\n", msg, parameter, ret); +- +- return 0; +-} +- +-static int vega10_get_argument(struct pp_hwmgr *hwmgr) +-{ +- struct amdgpu_device *adev = hwmgr->adev; +- +- return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); +-} +- + static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr, + uint8_t *table, int16_t table_id) + { +@@ -175,13 +44,13 @@ static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr, + "Invalid SMU Table version!", return -EINVAL); + PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, + "Invalid SMU Table Length!", return -EINVAL); +- vega10_send_msg_to_smc_with_parameter(hwmgr, ++ smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetDriverDramAddrHigh, + upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)); +- vega10_send_msg_to_smc_with_parameter(hwmgr, ++ smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetDriverDramAddrLow, + lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)); +- vega10_send_msg_to_smc_with_parameter(hwmgr, ++ smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_TransferTableSmu2Dram, + priv->smu_tables.entry[table_id].table_id); + +@@ -206,13 +75,13 @@ static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr, + memcpy(priv->smu_tables.entry[table_id].table, table, + priv->smu_tables.entry[table_id].size); + +- vega10_send_msg_to_smc_with_parameter(hwmgr, ++ smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetDriverDramAddrHigh, + upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)); +- vega10_send_msg_to_smc_with_parameter(hwmgr, ++ smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetDriverDramAddrLow, + lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)); +- vega10_send_msg_to_smc_with_parameter(hwmgr, ++ smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_TransferTableDram2Smu, + priv->smu_tables.entry[table_id].table_id); + +@@ -225,8 +94,8 @@ static int vega10_get_smc_features(struct pp_hwmgr *hwmgr, + if (features_enabled == NULL) + return -EINVAL; + +- vega10_send_msg_to_smc(hwmgr, PPSMC_MSG_GetEnabledSmuFeatures); +- *features_enabled = vega10_get_argument(hwmgr); ++ smu9_send_msg_to_smc(hwmgr, PPSMC_MSG_GetEnabledSmuFeatures); ++ *features_enabled = smu9_get_argument(hwmgr); + + return 0; + } +@@ -248,10 +117,10 @@ static int vega10_set_tools_address(struct pp_hwmgr *hwmgr) + struct vega10_smumgr *priv = hwmgr->smu_backend; + + if (priv->smu_tables.entry[TOOLSTABLE].mc_addr) { +- vega10_send_msg_to_smc_with_parameter(hwmgr, ++ smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetToolsDramAddrHigh, + upper_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr)); +- vega10_send_msg_to_smc_with_parameter(hwmgr, ++ smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetToolsDramAddrLow, + lower_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr)); + } +@@ -265,11 +134,11 @@ static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr) + uint32_t dev_id; + uint32_t rev_id; + +- PP_ASSERT_WITH_CODE(!vega10_send_msg_to_smc(hwmgr, ++ PP_ASSERT_WITH_CODE(!smu9_send_msg_to_smc(hwmgr, + PPSMC_MSG_GetDriverIfVersion), + "Attempt to get SMC IF Version Number Failed!", + return -EINVAL); +- smc_driver_if_version = vega10_get_argument(hwmgr); ++ smc_driver_if_version = smu9_get_argument(hwmgr); + + dev_id = adev->pdev->device; + rev_id = adev->pdev->revision; +@@ -441,7 +310,7 @@ static int vega10_smu_fini(struct pp_hwmgr *hwmgr) + + static int vega10_start_smu(struct pp_hwmgr *hwmgr) + { +- if (!vega10_is_smc_ram_running(hwmgr)) ++ if (!smu9_is_smc_ram_running(hwmgr)) + return -EINVAL; + + PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr), +@@ -453,7 +322,8 @@ static int vega10_start_smu(struct pp_hwmgr *hwmgr) + return 0; + } + +-static int vega10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw) ++static int vega10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, ++ uint16_t table_id, bool rw) + { + int ret; + +@@ -470,11 +340,11 @@ const struct pp_smumgr_func vega10_smu_funcs = { + .smu_fini = &vega10_smu_fini, + .start_smu = &vega10_start_smu, + .request_smu_load_specific_fw = NULL, +- .send_msg_to_smc = &vega10_send_msg_to_smc, +- .send_msg_to_smc_with_parameter = &vega10_send_msg_to_smc_with_parameter, ++ .send_msg_to_smc = &smu9_send_msg_to_smc, ++ .send_msg_to_smc_with_parameter = &smu9_send_msg_to_smc_with_parameter, + .download_pptable_settings = NULL, + .upload_pptable_settings = NULL, + .is_dpm_running = vega10_is_dpm_running, +- .get_argument = vega10_get_argument, ++ .get_argument = smu9_get_argument, + .smc_table_manager = vega10_smc_table_manager, + }; +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c +index 508a262..7f0e210 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c +@@ -24,157 +24,14 @@ + #include "smumgr.h" + #include "vega12_inc.h" + #include "soc15_common.h" ++#include "smu9_smumgr.h" + #include "vega12_smumgr.h" + #include "vega12_ppsmc.h" + #include "vega12/smu9_driver_if.h" +- + #include "ppatomctrl.h" + #include "pp_debug.h" + + +-/* MP Apertures */ +-#define MP0_Public 0x03800000 +-#define MP0_SRAM 0x03900000 +-#define MP1_Public 0x03b00000 +-#define MP1_SRAM 0x03c00004 +- +-#define smnMP1_FIRMWARE_FLAGS 0x3010028 +-#define smnMP0_FW_INTF 0x3010104 +-#define smnMP1_PUB_CTRL 0x3010b14 +- +-static bool vega12_is_smc_ram_running(struct pp_hwmgr *hwmgr) +-{ +- struct amdgpu_device *adev = hwmgr->adev; +- uint32_t mp1_fw_flags; +- +- WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2, +- (MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))); +- +- mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2); +- +- if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >> +- MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT) +- return true; +- +- return false; +-} +- +-/* +- * Check if SMC has responded to previous message. +- * +- * @param smumgr the address of the powerplay hardware manager. +- * @return TRUE SMC has responded, FALSE otherwise. +- */ +-static uint32_t vega12_wait_for_response(struct pp_hwmgr *hwmgr) +-{ +- struct amdgpu_device *adev = hwmgr->adev; +- uint32_t reg; +- +- reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); +- +- phm_wait_for_register_unequal(hwmgr, reg, +- 0, MP1_C2PMSG_90__CONTENT_MASK); +- +- return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90); +-} +- +-/* +- * Send a message to the SMC, and do not wait for its response. +- * @param smumgr the address of the powerplay hardware manager. +- * @param msg the message to send. +- * @return Always return 0. +- */ +-int vega12_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, +- uint16_t msg) +-{ +- struct amdgpu_device *adev = hwmgr->adev; +- +- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg); +- +- return 0; +-} +- +-/* +- * Send a message to the SMC, and wait for its response. +- * @param hwmgr the address of the powerplay hardware manager. +- * @param msg the message to send. +- * @return Always return 0. +- */ +-int vega12_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg) +-{ +- struct amdgpu_device *adev = hwmgr->adev; +- +- vega12_wait_for_response(hwmgr); +- +- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); +- +- vega12_send_msg_to_smc_without_waiting(hwmgr, msg); +- +- if (vega12_wait_for_response(hwmgr) != 1) +- pr_err("Failed to send message: 0x%x\n", msg); +- +- return 0; +-} +- +-/* +- * Send a message to the SMC with parameter +- * @param hwmgr: the address of the powerplay hardware manager. +- * @param msg: the message to send. +- * @param parameter: the parameter to send +- * @return Always return 0. +- */ +-int vega12_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, +- uint16_t msg, uint32_t parameter) +-{ +- struct amdgpu_device *adev = hwmgr->adev; +- +- vega12_wait_for_response(hwmgr); +- +- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0); +- +- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter); +- +- vega12_send_msg_to_smc_without_waiting(hwmgr, msg); +- +- if (vega12_wait_for_response(hwmgr) != 1) +- pr_err("Failed to send message: 0x%x\n", msg); +- +- return 0; +-} +- +- +-/* +- * Send a message to the SMC with parameter, do not wait for response +- * @param hwmgr: the address of the powerplay hardware manager. +- * @param msg: the message to send. +- * @param parameter: the parameter to send +- * @return The response that came from the SMC. +- */ +-int vega12_send_msg_to_smc_with_parameter_without_waiting( +- struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter) +-{ +- struct amdgpu_device *adev = hwmgr->adev; +- +- WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, parameter); +- +- return vega12_send_msg_to_smc_without_waiting(hwmgr, msg); +-} +- +-/* +- * Retrieve an argument from SMC. +- * @param hwmgr the address of the powerplay hardware manager. +- * @param arg pointer to store the argument from SMC. +- * @return Always return 0. +- */ +-int vega12_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg) +-{ +- struct amdgpu_device *adev = hwmgr->adev; +- +- *arg = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82); +- +- return 0; +-} +- + /* + * Copy table from SMC into driver FB + * @param hwmgr the address of the HW manager +@@ -192,16 +49,16 @@ int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr, + "Invalid SMU Table version!", return -EINVAL); + PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, + "Invalid SMU Table Length!", return -EINVAL); +- PP_ASSERT_WITH_CODE(vega12_send_msg_to_smc_with_parameter(hwmgr, ++ PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetDriverDramAddrHigh, + upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0, + "[CopyTableFromSMC] Attempt to Set Dram Addr High Failed!", return -EINVAL); +- PP_ASSERT_WITH_CODE(vega12_send_msg_to_smc_with_parameter(hwmgr, ++ PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetDriverDramAddrLow, + lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0, + "[CopyTableFromSMC] Attempt to Set Dram Addr Low Failed!", + return -EINVAL); +- PP_ASSERT_WITH_CODE(vega12_send_msg_to_smc_with_parameter(hwmgr, ++ PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_TransferTableSmu2Dram, + table_id) == 0, + "[CopyTableFromSMC] Attempt to Transfer Table From SMU Failed!", +@@ -234,17 +91,17 @@ int vega12_copy_table_to_smc(struct pp_hwmgr *hwmgr, + memcpy(priv->smu_tables.entry[table_id].table, table, + priv->smu_tables.entry[table_id].size); + +- PP_ASSERT_WITH_CODE(vega12_send_msg_to_smc_with_parameter(hwmgr, ++ PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetDriverDramAddrHigh, + upper_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0, + "[CopyTableToSMC] Attempt to Set Dram Addr High Failed!", + return -EINVAL;); +- PP_ASSERT_WITH_CODE(vega12_send_msg_to_smc_with_parameter(hwmgr, ++ PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetDriverDramAddrLow, + lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0, + "[CopyTableToSMC] Attempt to Set Dram Addr Low Failed!", + return -EINVAL); +- PP_ASSERT_WITH_CODE(vega12_send_msg_to_smc_with_parameter(hwmgr, ++ PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_TransferTableDram2Smu, + table_id) == 0, + "[CopyTableToSMC] Attempt to Transfer Table To SMU Failed!", +@@ -262,20 +119,20 @@ int vega12_enable_smc_features(struct pp_hwmgr *hwmgr, + smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); + + if (enable) { +- PP_ASSERT_WITH_CODE(vega12_send_msg_to_smc_with_parameter(hwmgr, ++ PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_EnableSmuFeaturesLow, smu_features_low) == 0, + "[EnableDisableSMCFeatures] Attemp to enable SMU features Low failed!", + return -EINVAL); +- PP_ASSERT_WITH_CODE(vega12_send_msg_to_smc_with_parameter(hwmgr, ++ PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_EnableSmuFeaturesHigh, smu_features_high) == 0, + "[EnableDisableSMCFeatures] Attemp to enable SMU features High failed!", + return -EINVAL); + } else { +- PP_ASSERT_WITH_CODE(vega12_send_msg_to_smc_with_parameter(hwmgr, ++ PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_DisableSmuFeaturesLow, smu_features_low) == 0, + "[EnableDisableSMCFeatures] Attemp to disable SMU features Low failed!", + return -EINVAL); +- PP_ASSERT_WITH_CODE(vega12_send_msg_to_smc_with_parameter(hwmgr, ++ PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_DisableSmuFeaturesHigh, smu_features_high) == 0, + "[EnableDisableSMCFeatures] Attemp to disable SMU features High failed!", + return -EINVAL); +@@ -292,22 +149,17 @@ int vega12_get_enabled_smc_features(struct pp_hwmgr *hwmgr, + if (features_enabled == NULL) + return -EINVAL; + +- PP_ASSERT_WITH_CODE(vega12_send_msg_to_smc(hwmgr, ++ PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc(hwmgr, + PPSMC_MSG_GetEnabledSmuFeaturesLow) == 0, + "[GetEnabledSMCFeatures] Attemp to get SMU features Low failed!", + return -EINVAL); +- PP_ASSERT_WITH_CODE(vega12_read_arg_from_smc(hwmgr, +- &smc_features_low) == 0, +- "[GetEnabledSMCFeatures] Attemp to read SMU features Low argument failed!", +- return -EINVAL); +- PP_ASSERT_WITH_CODE(vega12_send_msg_to_smc(hwmgr, ++ smc_features_low = smu9_get_argument(hwmgr); ++ ++ PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc(hwmgr, + PPSMC_MSG_GetEnabledSmuFeaturesHigh) == 0, + "[GetEnabledSMCFeatures] Attemp to get SMU features High failed!", + return -EINVAL); +- PP_ASSERT_WITH_CODE(vega12_read_arg_from_smc(hwmgr, +- &smc_features_high) == 0, +- "[GetEnabledSMCFeatures] Attemp to read SMU features High argument failed!", +- return -EINVAL); ++ smc_features_high = smu9_get_argument(hwmgr); + + *features_enabled = ((((uint64_t)smc_features_low << SMU_FEATURES_LOW_SHIFT) & SMU_FEATURES_LOW_MASK) | + (((uint64_t)smc_features_high << SMU_FEATURES_HIGH_SHIFT) & SMU_FEATURES_HIGH_MASK)); +@@ -333,10 +185,10 @@ static int vega12_set_tools_address(struct pp_hwmgr *hwmgr) + (struct vega12_smumgr *)(hwmgr->smu_backend); + + if (priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr) { +- if (!vega12_send_msg_to_smc_with_parameter(hwmgr, ++ if (!smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetToolsDramAddrHigh, + upper_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr))) +- vega12_send_msg_to_smc_with_parameter(hwmgr, ++ smu9_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetToolsDramAddrLow, + lower_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr)); + } +@@ -490,7 +342,7 @@ static int vega12_smu_fini(struct pp_hwmgr *hwmgr) + + static int vega12_start_smu(struct pp_hwmgr *hwmgr) + { +- PP_ASSERT_WITH_CODE(vega12_is_smc_ram_running(hwmgr), ++ PP_ASSERT_WITH_CODE(smu9_is_smc_ram_running(hwmgr), + "SMC is not running!", + return -EINVAL); + +@@ -504,9 +356,10 @@ const struct pp_smumgr_func vega12_smu_funcs = { + .smu_fini = &vega12_smu_fini, + .start_smu = &vega12_start_smu, + .request_smu_load_specific_fw = NULL, +- .send_msg_to_smc = &vega12_send_msg_to_smc, +- .send_msg_to_smc_with_parameter = &vega12_send_msg_to_smc_with_parameter, ++ .send_msg_to_smc = &smu9_send_msg_to_smc, ++ .send_msg_to_smc_with_parameter = &smu9_send_msg_to_smc_with_parameter, + .download_pptable_settings = NULL, + .upload_pptable_settings = NULL, + .is_dpm_running = vega12_is_dpm_running, ++ .get_argument = smu9_get_argument, + }; +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h +index 2810d38..b285cbc 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h +@@ -48,7 +48,6 @@ struct vega12_smumgr { + #define SMU_FEATURES_HIGH_MASK 0xFFFFFFFF00000000 + #define SMU_FEATURES_HIGH_SHIFT 32 + +-int vega12_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg); + int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr, + uint8_t *table, int16_t table_id); + int vega12_copy_table_to_smc(struct pp_hwmgr *hwmgr, +-- +2.7.4 + |