diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4927-drm-amd-display-Expose-bunch-of-functions-from-dcn10.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4927-drm-amd-display-Expose-bunch-of-functions-from-dcn10.patch | 173 |
1 files changed, 173 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4927-drm-amd-display-Expose-bunch-of-functions-from-dcn10.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4927-drm-amd-display-Expose-bunch-of-functions-from-dcn10.patch new file mode 100644 index 00000000..4d47ca1a --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4927-drm-amd-display-Expose-bunch-of-functions-from-dcn10.patch @@ -0,0 +1,173 @@ +From 7d608966251253c5424a41d644d10e7b4b81749c Mon Sep 17 00:00:00 2001 +From: Eric Bernstein <eric.bernstein@amd.com> +Date: Wed, 16 May 2018 16:19:50 -0400 +Subject: [PATCH 4927/5725] drm/amd/display: Expose bunch of functions from + dcn10_hw_sequencer + +v2: Remove spurious newline changes + +Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 59 +++++++++++++--------- + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 7 +++ + drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 8 +++ + 3 files changed, 49 insertions(+), 25 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 28dba6a..06cf967 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -849,7 +849,7 @@ static bool dcn10_hw_wa_force_recovery(struct dc *dc) + } + + +-static void dcn10_verify_allow_pstate_change_high(struct dc *dc) ++void dcn10_verify_allow_pstate_change_high(struct dc *dc) + { + static bool should_log_hw_state; /* prevent hw state log by default */ + +@@ -1863,8 +1863,7 @@ static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state) + dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params); + } + +- +-static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) ++static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx) + { + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct mpcc_blnd_cfg blnd_cfg; +@@ -2009,7 +2008,7 @@ static void update_dchubp_dpp( + + if (plane_state->update_flags.bits.full_update || + plane_state->update_flags.bits.per_pixel_alpha_change) +- update_mpcc(dc, pipe_ctx); ++ dc->hwss.update_mpcc(dc, pipe_ctx); + + if (plane_state->update_flags.bits.full_update || + plane_state->update_flags.bits.per_pixel_alpha_change || +@@ -2119,6 +2118,33 @@ static void set_hdr_multiplier(struct pipe_ctx *pipe_ctx) + pipe_ctx->plane_res.dpp, hw_mult); + } + ++void dcn10_program_pipe( ++ struct dc *dc, ++ struct pipe_ctx *pipe_ctx, ++ struct dc_state *context) ++{ ++ if (pipe_ctx->plane_state->update_flags.bits.full_update) ++ dcn10_enable_plane(dc, pipe_ctx, context); ++ ++ update_dchubp_dpp(dc, pipe_ctx, context); ++ ++ set_hdr_multiplier(pipe_ctx); ++ ++ if (pipe_ctx->plane_state->update_flags.bits.full_update || ++ pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || ++ pipe_ctx->plane_state->update_flags.bits.gamma_change) ++ dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); ++ ++ /* dcn10_translate_regamma_to_hw_format takes 750us to finish ++ * only do gamma programming for full update. ++ * TODO: This can be further optimized/cleaned up ++ * Always call this for now since it does memcmp inside before ++ * doing heavy calculation and programming ++ */ ++ if (pipe_ctx->plane_state->update_flags.bits.full_update) ++ dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); ++} ++ + static void program_all_pipe_in_tree( + struct dc *dc, + struct pipe_ctx *pipe_ctx, +@@ -2140,26 +2166,7 @@ static void program_all_pipe_in_tree( + } + + if (pipe_ctx->plane_state != NULL) { +- if (pipe_ctx->plane_state->update_flags.bits.full_update) +- dcn10_enable_plane(dc, pipe_ctx, context); +- +- update_dchubp_dpp(dc, pipe_ctx, context); +- +- set_hdr_multiplier(pipe_ctx); +- +- if (pipe_ctx->plane_state->update_flags.bits.full_update || +- pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || +- pipe_ctx->plane_state->update_flags.bits.gamma_change) +- dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state); +- +- /* dcn10_translate_regamma_to_hw_format takes 750us to finish +- * only do gamma programming for full update. +- * TODO: This can be further optimized/cleaned up +- * Always call this for now since it does memcmp inside before +- * doing heavy calculation and programming +- */ +- if (pipe_ctx->plane_state->update_flags.bits.full_update) +- dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream); ++ dcn10_program_pipe(dc, pipe_ctx, context); + } + + if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) { +@@ -2284,7 +2291,7 @@ static void dcn10_apply_ctx_for_surface( + old_pipe_ctx->plane_state && + old_pipe_ctx->stream_res.tg == tg) { + +- hwss1_plane_atomic_disconnect(dc, old_pipe_ctx); ++ dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx); + removed_pipe[i] = true; + + DC_LOG_DC("Reset mpcc for pipe %d\n", +@@ -2578,7 +2585,9 @@ static const struct hw_sequencer_funcs dcn10_funcs = { + .apply_ctx_to_hw = dce110_apply_ctx_to_hw, + .apply_ctx_for_surface = dcn10_apply_ctx_for_surface, + .update_plane_addr = dcn10_update_plane_addr, ++ .plane_atomic_disconnect = hwss1_plane_atomic_disconnect, + .update_dchub = dcn10_update_dchub, ++ .update_mpcc = dcn10_update_mpcc, + .update_pending_status = dcn10_update_pending_status, + .set_input_transfer_func = dcn10_set_input_transfer_func, + .set_output_transfer_func = dcn10_set_output_transfer_func, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +index 44f734b..7139fb7 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +@@ -39,4 +39,11 @@ bool is_rgb_cspace(enum dc_color_space output_color_space); + + void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx); + ++void dcn10_verify_allow_pstate_change_high(struct dc *dc); ++ ++void dcn10_program_pipe( ++ struct dc *dc, ++ struct pipe_ctx *pipe_ctx, ++ struct dc_state *context); ++ + #endif /* __DC_HWSS_DCN10_H__ */ +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +index 2506601..c2277d1 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +@@ -102,10 +102,18 @@ struct hw_sequencer_funcs { + const struct dc *dc, + struct pipe_ctx *pipe_ctx); + ++ void (*plane_atomic_disconnect)( ++ struct dc *dc, ++ struct pipe_ctx *pipe_ctx); ++ + void (*update_dchub)( + struct dce_hwseq *hws, + struct dchub_init_data *dh_data); + ++ void (*update_mpcc)( ++ struct dc *dc, ++ struct pipe_ctx *pipe_ctx); ++ + void (*update_pending_status)( + struct pipe_ctx *pipe_ctx); + +-- +2.7.4 + |