diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4899-drm-amd-display-generic-indirect-register-access.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4899-drm-amd-display-generic-indirect-register-access.patch | 136 |
1 files changed, 136 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4899-drm-amd-display-generic-indirect-register-access.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4899-drm-amd-display-generic-indirect-register-access.patch new file mode 100644 index 00000000..187a1d7b --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4899-drm-amd-display-generic-indirect-register-access.patch @@ -0,0 +1,136 @@ +From b5cce50c1cbbb46ec3b9fb1d87cfefd974f3ed69 Mon Sep 17 00:00:00 2001 +From: Tony Cheng <tony.cheng@amd.com> +Date: Sat, 16 Jun 2018 19:43:41 -0400 +Subject: [PATCH 4899/5725] drm/amd/display: generic indirect register access + +add generic indirect register access following our register access pattern + +this will make it easier to review code and programming sequence, +with all the complexity hidden in macro + +Signed-off-by: Tony Cheng <tony.cheng@amd.com> +Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dc_helper.c | 51 +++++++++++++++++++++++++ + drivers/gpu/drm/amd/display/dc/inc/reg_helper.h | 46 ++++++++++++++++++++++ + 2 files changed, 97 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c +index bd0fda0..e68077e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c ++++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c +@@ -255,3 +255,54 @@ uint32_t generic_reg_wait(const struct dc_context *ctx, + + return reg_val; + } ++ ++void generic_write_indirect_reg(const struct dc_context *ctx, ++ uint32_t addr_index, uint32_t addr_data, ++ uint32_t index, uint32_t data) ++{ ++ dm_write_reg(ctx, addr_index, index); ++ dm_write_reg(ctx, addr_data, data); ++} ++ ++uint32_t generic_read_indirect_reg(const struct dc_context *ctx, ++ uint32_t addr_index, uint32_t addr_data, ++ uint32_t index) ++{ ++ uint32_t value = 0; ++ ++ dm_write_reg(ctx, addr_index, index); ++ value = dm_read_reg(ctx, addr_data); ++ ++ return value; ++} ++ ++ ++uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx, ++ uint32_t addr_index, uint32_t addr_data, ++ uint32_t index, uint32_t reg_val, int n, ++ uint8_t shift1, uint32_t mask1, uint32_t field_value1, ++ ...) ++{ ++ uint32_t shift, mask, field_value; ++ int i = 1; ++ ++ va_list ap; ++ ++ va_start(ap, field_value1); ++ ++ reg_val = set_reg_field_value_ex(reg_val, field_value1, mask1, shift1); ++ ++ while (i < n) { ++ shift = va_arg(ap, uint32_t); ++ mask = va_arg(ap, uint32_t); ++ field_value = va_arg(ap, uint32_t); ++ ++ reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift); ++ i++; ++ } ++ ++ generic_write_indirect_reg(ctx, addr_index, addr_data, index, reg_val); ++ va_end(ap); ++ ++ return reg_val; ++} +diff --git a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h +index 3306e7b..cf5a84b 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/reg_helper.h +@@ -445,4 +445,50 @@ uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr, + uint8_t shift6, uint32_t mask6, uint32_t *field_value6, + uint8_t shift7, uint32_t mask7, uint32_t *field_value7, + uint8_t shift8, uint32_t mask8, uint32_t *field_value8); ++ ++ ++/* indirect register access */ ++ ++#define IX_REG_SET_N(index_reg_name, data_reg_name, index, n, initial_val, ...) \ ++ generic_indirect_reg_update_ex(CTX, \ ++ REG(index_reg_name), REG(data_reg_name), IND_REG(index), \ ++ initial_val, \ ++ n, __VA_ARGS__) ++ ++#define IX_REG_SET_2(index_reg_name, data_reg_name, index, init_value, f1, v1, f2, v2) \ ++ IX_REG_SET_N(index_reg_name, data_reg_name, index, 2, init_value, \ ++ FN(reg, f1), v1,\ ++ FN(reg, f2), v2) ++ ++ ++#define IX_REG_READ(index_reg_name, data_reg_name, index) \ ++ generic_read_indirect_reg(CTX, REG(index_reg_name), REG(data_reg_name), IND_REG(index)) ++ ++ ++ ++#define IX_REG_UPDATE_N(index_reg_name, data_reg_name, index, n, ...) \ ++ generic_indirect_reg_update_ex(CTX, \ ++ REG(index_reg_name), REG(data_reg_name), IND_REG(index), \ ++ IX_REG_READ(index_reg_name, data_reg_name, index), \ ++ n, __VA_ARGS__) ++ ++#define IX_REG_UPDATE_2(index_reg_name, data_reg_name, index, f1, v1, f2, v2) \ ++ IX_REG_UPDATE_N(index_reg_name, data_reg_name, index, 2,\ ++ FN(reg, f1), v1,\ ++ FN(reg, f2), v2) ++ ++void generic_write_indirect_reg(const struct dc_context *ctx, ++ uint32_t addr_index, uint32_t addr_data, ++ uint32_t index, uint32_t data); ++ ++uint32_t generic_read_indirect_reg(const struct dc_context *ctx, ++ uint32_t addr_index, uint32_t addr_data, ++ uint32_t index); ++ ++uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx, ++ uint32_t addr_index, uint32_t addr_data, ++ uint32_t index, uint32_t reg_val, int n, ++ uint8_t shift1, uint32_t mask1, uint32_t field_value1, ++ ...); ++ + #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */ +-- +2.7.4 + |