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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4886-drm-amd-Use-newly-added-interrupt-source-defs-for-SO.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/4886-drm-amd-Use-newly-added-interrupt-source-defs-for-SO.patch226
1 files changed, 226 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4886-drm-amd-Use-newly-added-interrupt-source-defs-for-SO.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4886-drm-amd-Use-newly-added-interrupt-source-defs-for-SO.patch
new file mode 100644
index 00000000..f8195b3e
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4886-drm-amd-Use-newly-added-interrupt-source-defs-for-SO.patch
@@ -0,0 +1,226 @@
+From 2cc1f3ad95b6563f7c090bc9af8dbeb8b568cf59 Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 25 May 2018 10:45:34 -0400
+Subject: [PATCH 4886/5725] drm/amd: Use newly added interrupt source defs for
+ SOC15.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++----
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 ++++--
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 7 +++++--
+ drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 5 +++--
+ drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 2 ++
+ drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 ++++--
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c | 8 +++++---
+ 7 files changed, 29 insertions(+), 15 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+index e221eb0..39b229e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+@@ -38,6 +38,8 @@
+ #include "clearstate_gfx9.h"
+ #include "v9_structs.h"
+
++#include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
++
+ #define GFX9_NUM_GFX_RINGS 1
+ #define GFX9_MEC_HPD_SIZE 2048
+ #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
+@@ -1500,23 +1502,23 @@ static int gfx_v9_0_sw_init(void *handle)
+ adev->gfx.mec.num_queue_per_pipe = 8;
+
+ /* KIQ event */
+- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
++ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_IB2_INTERRUPT_PKT, &adev->gfx.kiq.irq);
+ if (r)
+ return r;
+
+ /* EOP Event */
+- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
++ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
+ if (r)
+ return r;
+
+ /* Privileged reg */
+- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 184,
++ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
+ &adev->gfx.priv_reg_irq);
+ if (r)
+ return r;
+
+ /* Privileged inst */
+- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 185,
++ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
+ &adev->gfx.priv_inst_irq);
+ if (r)
+ return r;
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 95b0587..5255647 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -42,6 +42,8 @@
+ #include "gfxhub_v1_0.h"
+ #include "mmhub_v1_0.h"
+
++#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
++
+ /* add these here since we already include dce12 headers and these are for DCN */
+ #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
+ #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
+@@ -877,9 +879,9 @@ static int gmc_v9_0_sw_init(void *handle)
+ }
+
+ /* This interrupt is VMC page fault.*/
+- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, 0,
++ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
+ &adev->gmc.vm_fault);
+- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, 0,
++ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
+ &adev->gmc.vm_fault);
+
+ if (r)
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+index 55d2c17..d102712 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+@@ -38,6 +38,9 @@
+ #include "soc15.h"
+ #include "vega10_sdma_pkt_open.h"
+
++#include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
++#include "ivsrcid/sdma1/irqsrcs_sdma1_4_0.h"
++
+ MODULE_FIRMWARE("amdgpu/vega10_sdma.bin");
+ MODULE_FIRMWARE("amdgpu/vega10_sdma1.bin");
+ MODULE_FIRMWARE("amdgpu/vega12_sdma.bin");
+@@ -1229,13 +1232,13 @@ static int sdma_v4_0_sw_init(void *handle)
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ /* SDMA trap event */
+- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 224,
++ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, SDMA0_4_0__SRCID__SDMA_TRAP,
+ &adev->sdma.trap_irq);
+ if (r)
+ return r;
+
+ /* SDMA trap event */
+- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 224,
++ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, SDMA1_4_0__SRCID__SDMA_TRAP,
+ &adev->sdma.trap_irq);
+ if (r)
+ return r;
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+index 78b5111..07f5ccb 100644
+--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+@@ -39,6 +39,7 @@
+ #include "hdp/hdp_4_0_offset.h"
+ #include "mmhub/mmhub_1_0_offset.h"
+ #include "mmhub/mmhub_1_0_sh_mask.h"
++#include "ivsrcid/uvd/irqsrcs_uvd_7_0.h"
+
+ #define UVD7_MAX_HW_INSTANCES_VEGA20 2
+
+@@ -402,13 +403,13 @@ static int uvd_v7_0_sw_init(void *handle)
+
+ for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
+ /* UVD TRAP */
+- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], 124, &adev->uvd.inst[j].irq);
++ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq);
+ if (r)
+ return r;
+
+ /* UVD ENC TRAP */
+ for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+- r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + 119, &adev->uvd.inst[j].irq);
++ r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq);
+ if (r)
+ return r;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+index 575bf97..65f8860 100755
+--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+@@ -39,6 +39,8 @@
+ #include "mmhub/mmhub_1_0_offset.h"
+ #include "mmhub/mmhub_1_0_sh_mask.h"
+
++#include "ivsrcid/vce/irqsrcs_vce_4_0.h"
++
+ #define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
+
+ #define VCE_V4_0_FW_SIZE (384 * 1024)
+diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+index 7bca18b..90103b0 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+@@ -35,6 +35,8 @@
+ #include "mmhub/mmhub_9_1_offset.h"
+ #include "mmhub/mmhub_9_1_sh_mask.h"
+
++#include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
++
+ static int vcn_v1_0_stop(struct amdgpu_device *adev);
+ static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
+ static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
+@@ -77,13 +79,13 @@ static int vcn_v1_0_sw_init(void *handle)
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ /* VCN DEC TRAP */
+- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 124, &adev->vcn.irq);
++ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.irq);
+ if (r)
+ return r;
+
+ /* VCN ENC TRAP */
+ for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
+- r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + 119,
++ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
+ &adev->vcn.irq);
+ if (r)
+ return r;
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
+index 3effb55..8eea49e 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c
+@@ -25,6 +25,8 @@
+ #include "ppatomctrl.h"
+ #include "ppsmc.h"
+ #include "atom.h"
++#include "ivsrcid/thm/irqsrcs_thm_9_0.h"
++#include "ivsrcid/smuio/irqsrcs_smuio_9_0.h"
+
+ uint8_t convert_to_vid(uint16_t vddc)
+ {
+@@ -594,17 +596,17 @@ int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr)
+
+ amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+ SOC15_IH_CLIENTID_THM,
+- 0,
++ THM_9_0__SRCID__THM_DIG_THERM_L2H,
+ source);
+ amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+ SOC15_IH_CLIENTID_THM,
+- 1,
++ THM_9_0__SRCID__THM_DIG_THERM_H2L,
+ source);
+
+ /* Register CTF(GPIO_19) interrupt */
+ amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+ SOC15_IH_CLIENTID_ROM_SMUIO,
+- 83,
++ SMUIO_9_0__SRCID__SMUIO_GPIO19,
+ source);
+
+ return 0;
+--
+2.7.4
+