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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4884-drm-amd-Use-newly-added-interrupt-source-defs-for-VI.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/4884-drm-amd-Use-newly-added-interrupt-source-defs-for-VI.patch391
1 files changed, 391 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4884-drm-amd-Use-newly-added-interrupt-source-defs-for-VI.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4884-drm-amd-Use-newly-added-interrupt-source-defs-for-VI.patch
new file mode 100644
index 00000000..7301c4cb
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4884-drm-amd-Use-newly-added-interrupt-source-defs-for-VI.patch
@@ -0,0 +1,391 @@
+From 7de2293f66c15dd769d1dfe92274d51a04ddd52f Mon Sep 17 00:00:00 2001
+From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Date: Fri, 25 May 2018 10:06:52 -0400
+Subject: [PATCH 4884/5725] drm/amd: Use newly added interrupt source defs for
+ VI v3.
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+v2: Rebase
+v3: Use defines for CP_SQ and CP_ECC_ERROR interrupts.
+
+Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 ++++--
+ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 ++++--
+ drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++------
+ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 6 ++++--
+ drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 6 ++++--
+ drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 6 ++++--
+ drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 6 ++++--
+ drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 3 ++-
+ drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 +++--
+ drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 ++-
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 8 +++++---
+ 12 files changed, 46 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+index f9f9165..85649e9 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+@@ -41,6 +41,8 @@
+ #include "gmc/gmc_8_1_d.h"
+ #include "gmc/gmc_8_1_sh_mask.h"
+
++#include "ivsrcid/ivsrcid_vislands30.h"
++
+ static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
+ static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
+
+@@ -2744,14 +2746,14 @@ static int dce_v10_0_sw_init(void *handle)
+ return r;
+ }
+
+- for (i = 8; i < 20; i += 2) {
++ for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
+ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
+ if (r)
+ return r;
+ }
+
+ /* HPD hotplug */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
+ if (r)
+ return r;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+index b123a99..4e4e5fc 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+@@ -41,6 +41,8 @@
+ #include "gmc/gmc_8_1_d.h"
+ #include "gmc/gmc_8_1_sh_mask.h"
+
++#include "ivsrcid/ivsrcid_vislands30.h"
++
+ static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
+ static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
+
+@@ -2866,14 +2868,14 @@ static int dce_v11_0_sw_init(void *handle)
+ return r;
+ }
+
+- for (i = 8; i < 20; i += 2) {
++ for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
+ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
+ if (r)
+ return r;
+ }
+
+ /* HPD hotplug */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
+ if (r)
+ return r;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+index 28bf8cf..7145e7a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
++++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
+@@ -36,6 +36,7 @@
+ #include "dce_v10_0.h"
+ #include "dce_v11_0.h"
+ #include "dce_virtual.h"
++#include "ivsrcid/ivsrcid_vislands30.h"
+
+ #define DCE_VIRTUAL_VBLANK_PERIOD 16666666
+
+@@ -381,7 +382,7 @@ static int dce_virtual_sw_init(void *handle)
+ int r, i;
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 229, &adev->crtc_irq);
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER, &adev->crtc_irq);
+ if (r)
+ return r;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+index 92bda71..96d517e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+@@ -51,6 +51,8 @@
+
+ #include "smu/smu_7_1_3_d.h"
+
++#include "ivsrcid/ivsrcid_vislands30.h"
++
+ #define GFX8_NUM_GFX_RINGS 1
+ #define GFX8_MEC_HPD_SIZE 2048
+
+@@ -2046,35 +2048,35 @@ static int gfx_v8_0_sw_init(void *handle)
+ adev->gfx.mec.num_queue_per_pipe = 8;
+
+ /* KIQ event */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 178, &adev->gfx.kiq.irq);
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_INT_IB2, &adev->gfx.kiq.irq);
+ if (r)
+ return r;
+
+ /* EOP Event */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
+ if (r)
+ return r;
+
+ /* Privileged reg */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184,
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT,
+ &adev->gfx.priv_reg_irq);
+ if (r)
+ return r;
+
+ /* Privileged inst */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185,
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT,
+ &adev->gfx.priv_inst_irq);
+ if (r)
+ return r;
+
+ /* Add CP EDC/ECC irq */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 197,
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR,
+ &adev->gfx.cp_ecc_error_irq);
+ if (r)
+ return r;
+
+ /* SQ interrupts. */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 239,
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG,
+ &adev->gfx.sq_irq);
+ if (r) {
+ DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+index 4fd4081..3040e8a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+@@ -43,6 +43,8 @@
+
+ #include "amdgpu_atombios.h"
+
++#include "ivsrcid/ivsrcid_vislands30.h"
++
+ static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);
+ static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
+ static int gmc_v7_0_wait_for_idle(void *handle);
+@@ -998,11 +1000,11 @@ static int gmc_v7_0_sw_init(void *handle)
+ adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
+ }
+
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
+ if (r)
+ return r;
+
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
+ if (r)
+ return r;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+index a3312f7..5476ddd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+@@ -44,6 +44,8 @@
+
+ #include "amdgpu_atombios.h"
+
++#include "ivsrcid/ivsrcid_vislands30.h"
++
+ static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
+ static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
+ static int gmc_v8_0_wait_for_idle(void *handle);
+@@ -1106,11 +1108,11 @@ static int gmc_v8_0_sw_init(void *handle)
+ adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
+ }
+
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
+ if (r)
+ return r;
+
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
+ if (r)
+ return r;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+index 096c6f2..cc22269 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+@@ -44,6 +44,8 @@
+
+ #include "iceland_sdma_pkt_open.h"
+
++#include "ivsrcid/ivsrcid_vislands30.h"
++
+ static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
+ static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
+ static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
+@@ -903,7 +905,7 @@ static int sdma_v2_4_sw_init(void *handle)
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ /* SDMA trap event */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224,
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
+ &adev->sdma.trap_irq);
+ if (r)
+ return r;
+@@ -915,7 +917,7 @@ static int sdma_v2_4_sw_init(void *handle)
+ return r;
+
+ /* SDMA Privileged inst */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247,
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
+ &adev->sdma.illegal_inst_irq);
+ if (r)
+ return r;
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+index e074dea..4b7df45 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+@@ -44,6 +44,8 @@
+
+ #include "tonga_sdma_pkt_open.h"
+
++#include "ivsrcid/ivsrcid_vislands30.h"
++
+ static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
+ static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
+ static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
+@@ -1183,7 +1185,7 @@ static int sdma_v3_0_sw_init(void *handle)
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ /* SDMA trap event */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224,
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
+ &adev->sdma.trap_irq);
+ if (r)
+ return r;
+@@ -1195,7 +1197,7 @@ static int sdma_v3_0_sw_init(void *handle)
+ return r;
+
+ /* SDMA Privileged inst */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247,
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
+ &adev->sdma.illegal_inst_irq);
+ if (r)
+ return r;
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+index 693944f..ab3ad86 100644
+--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+@@ -35,6 +35,7 @@
+ #include "vi.h"
+ #include "smu/smu_7_1_2_d.h"
+ #include "smu/smu_7_1_2_sh_mask.h"
++#include "ivsrcid/ivsrcid_vislands30.h"
+
+ static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev);
+ static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev);
+@@ -104,7 +105,7 @@ static int uvd_v5_0_sw_init(void *handle)
+ int r;
+
+ /* UVD TRAP */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
+ if (r)
+ return r;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+index 6f008a0..bca9c63 100644
+--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+@@ -36,6 +36,7 @@
+ #include "bif/bif_5_1_d.h"
+ #include "gmc/gmc_8_1_d.h"
+ #include "vi.h"
++#include "ivsrcid/ivsrcid_vislands30.h"
+
+ /* Polaris10/11/12 firmware version */
+ #define FW_1_130_16 ((1 << 24) | (130 << 16) | (16 << 8))
+@@ -400,14 +401,14 @@ static int uvd_v6_0_sw_init(void *handle)
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+ /* UVD TRAP */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
+ if (r)
+ return r;
+
+ /* UVD ENC TRAP */
+ if (uvd_v6_0_enc_support(adev)) {
+ for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 119, &adev->uvd.inst->irq);
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
+ if (r)
+ return r;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+index 99604d0..cc6ce6c 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+@@ -39,6 +39,7 @@
+ #include "smu/smu_7_1_2_sh_mask.h"
+ #include "gca/gfx_8_0_d.h"
+ #include "gca/gfx_8_0_sh_mask.h"
++#include "ivsrcid/ivsrcid_vislands30.h"
+
+
+ #define GRBM_GFX_INDEX__VCE_INSTANCE__SHIFT 0x04
+@@ -422,7 +423,7 @@ static int vce_v3_0_sw_init(void *handle)
+ int r, i;
+
+ /* VCE */
+- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 167, &adev->vce.irq);
++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_VCE_TRAP, &adev->vce.irq);
+ if (r)
+ return r;
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+index 47a4bbc..e3c1eb4 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+@@ -48,6 +48,8 @@
+ #include "processpptables.h"
+ #include "pp_thermal.h"
+
++#include "ivsrcid/ivsrcid_vislands30.h"
++
+ #define MC_CG_ARB_FREQ_F0 0x0a
+ #define MC_CG_ARB_FREQ_F1 0x0b
+ #define MC_CG_ARB_FREQ_F2 0x0c
+@@ -4105,17 +4107,17 @@ static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
+
+ amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+ AMDGPU_IH_CLIENTID_LEGACY,
+- 230,
++ VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH,
+ source);
+ amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+ AMDGPU_IH_CLIENTID_LEGACY,
+- 231,
++ VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW,
+ source);
+
+ /* Register CTF(GPIO_19) interrupt */
+ amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
+ AMDGPU_IH_CLIENTID_LEGACY,
+- 83,
++ VISLANDS30_IV_SRCID_GPIO_19,
+ source);
+
+ return 0;
+--
+2.7.4
+