diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4869-drm-amd-pp-Send-khz-clock-values-to-DC-for-smu7-8.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4869-drm-amd-pp-Send-khz-clock-values-to-DC-for-smu7-8.patch | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4869-drm-amd-pp-Send-khz-clock-values-to-DC-for-smu7-8.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4869-drm-amd-pp-Send-khz-clock-values-to-DC-for-smu7-8.patch new file mode 100644 index 00000000..9ead0b59 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4869-drm-amd-pp-Send-khz-clock-values-to-DC-for-smu7-8.patch @@ -0,0 +1,86 @@ +From 8ce31c35f040ae082511a37263d87ae42aa9edcf Mon Sep 17 00:00:00 2001 +From: Harry Wentland <harry.wentland@amd.com> +Date: Mon, 9 Jul 2018 13:48:12 -0400 +Subject: [PATCH 4869/5725] drm/amd/pp: Send khz clock values to DC for smu7/8 + +The previous change wasn't covering smu 7 and 8 and therefore DC was +seeing wrong clock values. + +This fixes an issue where the pipes seem to hang with a 4k DP and 1080p +HDMI display. + +Fixes: c3df50abc84b ("drm/amd/pp: Convert clock unit to KHz as defined") +Signed-off-by: Harry Wentland <harry.wentland@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +Cc:rex.zhu@amd.com +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 8 ++++---- + drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c | 6 +++--- + 2 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index b57a5df..47a4bbc 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -4610,12 +4610,12 @@ static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) + return -EINVAL; + dep_sclk_table = table_info->vdd_dep_on_sclk; + for (i = 0; i < dep_sclk_table->count; i++) +- clocks->clock[i] = dep_sclk_table->entries[i].clk; ++ clocks->clock[i] = dep_sclk_table->entries[i].clk * 10; + clocks->count = dep_sclk_table->count; + } else if (hwmgr->pp_table_version == PP_TABLE_V0) { + sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; + for (i = 0; i < sclk_table->count; i++) +- clocks->clock[i] = sclk_table->entries[i].clk; ++ clocks->clock[i] = sclk_table->entries[i].clk * 10; + clocks->count = sclk_table->count; + } + +@@ -4647,7 +4647,7 @@ static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) + return -EINVAL; + dep_mclk_table = table_info->vdd_dep_on_mclk; + for (i = 0; i < dep_mclk_table->count; i++) { +- clocks->clock[i] = dep_mclk_table->entries[i].clk; ++ clocks->clock[i] = dep_mclk_table->entries[i].clk * 10; + clocks->latency[i] = smu7_get_mem_latency(hwmgr, + dep_mclk_table->entries[i].clk); + } +@@ -4655,7 +4655,7 @@ static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) + } else if (hwmgr->pp_table_version == PP_TABLE_V0) { + mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk; + for (i = 0; i < mclk_table->count; i++) +- clocks->clock[i] = mclk_table->entries[i].clk; ++ clocks->clock[i] = mclk_table->entries[i].clk * 10; + clocks->count = mclk_table->count; + } + return 0; +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c +index 50690c7..288802f 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c +@@ -1604,17 +1604,17 @@ static int smu8_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type + switch (type) { + case amd_pp_disp_clock: + for (i = 0; i < clocks->count; i++) +- clocks->clock[i] = data->sys_info.display_clock[i]; ++ clocks->clock[i] = data->sys_info.display_clock[i] * 10; + break; + case amd_pp_sys_clock: + table = hwmgr->dyn_state.vddc_dependency_on_sclk; + for (i = 0; i < clocks->count; i++) +- clocks->clock[i] = table->entries[i].clk; ++ clocks->clock[i] = table->entries[i].clk * 10; + break; + case amd_pp_mem_clock: + clocks->count = SMU8_NUM_NBPMEMORYCLOCK; + for (i = 0; i < clocks->count; i++) +- clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i]; ++ clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i] * 10; + break; + default: + return -1; +-- +2.7.4 + |