aboutsummaryrefslogtreecommitdiffstats
path: root/common/recipes-kernel/linux/linux-yocto-4.14.71/4850-drm-amdgpu-use-pcie-functions-for-link-width-and-spe.patch
diff options
context:
space:
mode:
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4850-drm-amdgpu-use-pcie-functions-for-link-width-and-spe.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/4850-drm-amdgpu-use-pcie-functions-for-link-width-and-spe.patch341
1 files changed, 341 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4850-drm-amdgpu-use-pcie-functions-for-link-width-and-spe.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4850-drm-amdgpu-use-pcie-functions-for-link-width-and-spe.patch
new file mode 100644
index 00000000..c3257d6c
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4850-drm-amdgpu-use-pcie-functions-for-link-width-and-spe.patch
@@ -0,0 +1,341 @@
+From 85ca399974d01aa27b21b393a70a04b30cfc5e09 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 25 Jun 2018 13:07:50 -0500
+Subject: [PATCH 4850/5725] drm/amdgpu: use pcie functions for link width and
+ speed
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use the newly exported pci functions to get the link width
+and speed rather than using the drm duplicated versions.
+
+Also query the GPU link caps directly rather than hardcoding
+them.
+
+Acked-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Raveendra Talabattula <raveendra.talabattula@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 83 +++++++++++++++++++++---------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 7 ++-
+ drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 3 +-
+ drivers/gpu/drm/amd/amdgpu/si_dpm.c | 3 +-
+ drivers/pci/pci.c | 63 +++++++++++++++++++++++
+ include/linux/pci.h | 4 ++
+ include/uapi/linux/pci_regs.h | 2 +
+ 7 files changed, 134 insertions(+), 31 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index c0c835a..88c3879 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3374,8 +3374,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
+ */
+ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
+ {
+- u32 mask;
+- int ret;
++ struct pci_dev *pdev;
++ enum pci_bus_speed speed_cap;
++ enum pcie_link_width link_width;
+
+ if (amdgpu_pcie_gen_cap)
+ adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
+@@ -3393,27 +3394,61 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
+ }
+
+ if (adev->pm.pcie_gen_mask == 0) {
+- ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
+- if (!ret) {
+- adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
++ /* asic caps */
++ pdev = adev->pdev;
++ speed_cap = pcie_get_speed_cap(pdev);
++ if (speed_cap == PCI_SPEED_UNKNOWN) {
++ adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
+ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
+-
+- if (mask & DRM_PCIE_SPEED_25)
+- adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
+- if (mask & DRM_PCIE_SPEED_50)
+- adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
+- if (mask & DRM_PCIE_SPEED_80)
+- adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
+ } else {
+- adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
++ if (speed_cap == PCIE_SPEED_16_0GT)
++ adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
++ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
++ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 |
++ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4);
++ else if (speed_cap == PCIE_SPEED_8_0GT)
++ adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
++ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
++ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
++ else if (speed_cap == PCIE_SPEED_5_0GT)
++ adev->pm.pcie_gen_mask |= (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
++ CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2);
++ else
++ adev->pm.pcie_gen_mask |= CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1;
++ }
++ /* platform caps */
++ pdev = adev->ddev->pdev->bus->self;
++ speed_cap = pcie_get_speed_cap(pdev);
++ if (speed_cap == PCI_SPEED_UNKNOWN) {
++ adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
++ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
++ } else {
++ if (speed_cap == PCIE_SPEED_16_0GT)
++ adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
++ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
++ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 |
++ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4);
++ else if (speed_cap == PCIE_SPEED_8_0GT)
++ adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
++ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
++ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3);
++ else if (speed_cap == PCIE_SPEED_5_0GT)
++ adev->pm.pcie_gen_mask |= (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 |
++ CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2);
++ else
++ adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
++
+ }
+ }
+ if (adev->pm.pcie_mlw_mask == 0) {
+- ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
+- if (!ret) {
+- switch (mask) {
+- case 32:
++ pdev = adev->ddev->pdev->bus->self;
++ link_width = pcie_get_width_cap(pdev);
++ if (link_width == PCIE_LNK_WIDTH_UNKNOWN) {
++ adev->pm.pcie_mlw_mask |= AMDGPU_DEFAULT_PCIE_MLW_MASK;
++ } else {
++ switch (link_width) {
++ case PCIE_LNK_X32:
+ adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
+@@ -3422,7 +3457,7 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
+ break;
+- case 16:
++ case PCIE_LNK_X16:
+ adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
+@@ -3430,36 +3465,34 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev)
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
+ break;
+- case 12:
++ case PCIE_LNK_X12:
+ adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
+ break;
+- case 8:
++ case PCIE_LNK_X8:
+ adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
+ break;
+- case 4:
++ case PCIE_LNK_X4:
+ adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
+ break;
+- case 2:
++ case PCIE_LNK_X2:
+ adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
+ CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
+ break;
+- case 1:
++ case PCIE_LNK_X1:
+ adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
+ break;
+ default:
+ break;
+ }
+- } else {
+- adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
+ }
+ }
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+index def1010..719061f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+@@ -28,6 +28,7 @@
+ #include "amdgpu_i2c.h"
+ #include "amdgpu_dpm.h"
+ #include "atom.h"
++#include "amd_pcie.h"
+
+ void amdgpu_dpm_print_class_info(u32 class, u32 class2)
+ {
+@@ -936,9 +937,11 @@ enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev,
+ case AMDGPU_PCIE_GEN3:
+ return AMDGPU_PCIE_GEN3;
+ default:
+- if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
++ if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) &&
++ (default_gen == AMDGPU_PCIE_GEN3))
+ return AMDGPU_PCIE_GEN3;
+- else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
++ else if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) &&
++ (default_gen == AMDGPU_PCIE_GEN2))
+ return AMDGPU_PCIE_GEN2;
+ else
+ return AMDGPU_PCIE_GEN1;
+diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+index caaaabf..9bf0b24 100644
+--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
++++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+@@ -5845,8 +5845,7 @@ static int ci_dpm_init(struct amdgpu_device *adev)
+ adev->pm.dpm.priv = pi;
+
+ pi->sys_pcie_mask =
+- (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
+- CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
++ adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
+
+ pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+index 1026431..a32f6f6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
++++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+@@ -7317,8 +7317,7 @@ static int si_dpm_init(struct amdgpu_device *adev)
+ pi = &eg_pi->rv7xx;
+
+ si_pi->sys_pcie_mask =
+- (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >>
+- CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT;
++ adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
+ si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
+ si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
+
+diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
+index 1dde9da..f0957d4 100755
+--- a/drivers/pci/pci.c
++++ b/drivers/pci/pci.c
+@@ -5156,6 +5156,69 @@ int pcie_set_mps(struct pci_dev *dev, int mps)
+ EXPORT_SYMBOL(pcie_set_mps);
+
+ /**
++ * pcie_get_speed_cap - query for the PCI device's link speed capability
++ * @dev: PCI device to query
++ *
++ * Query the PCI device speed capability. Return the maximum link speed
++ * supported by the device.
++ */
++enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
++{
++ u32 lnkcap2, lnkcap;
++
++ /*
++ * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link
++ * Speeds Vector in Link Capabilities 2 when supported, falling
++ * back to Max Link Speed in Link Capabilities otherwise.
++ */
++ pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
++ if (lnkcap2) { /* PCIe r3.0-compliant */
++ if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
++ return PCIE_SPEED_16_0GT;
++ else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
++ return PCIE_SPEED_8_0GT;
++ else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
++ return PCIE_SPEED_5_0GT;
++ else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
++ return PCIE_SPEED_2_5GT;
++ return PCI_SPEED_UNKNOWN;
++ }
++ pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
++ if (lnkcap) {
++ if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
++ return PCIE_SPEED_16_0GT;
++ else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
++ return PCIE_SPEED_8_0GT;
++ else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
++ return PCIE_SPEED_5_0GT;
++ else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
++ return PCIE_SPEED_2_5GT;
++ }
++
++ return PCI_SPEED_UNKNOWN;
++}
++EXPORT_SYMBOL(pcie_get_speed_cap);
++
++/**
++ * pcie_get_width_cap - query for the PCI device's link width capability
++ * @dev: PCI device to query
++ *
++ * Query the PCI device width capability. Return the maximum link width
++ * supported by the device.
++ */
++enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
++{
++ u32 lnkcap;
++
++ pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
++ if (lnkcap)
++ return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
++
++ return PCIE_LNK_WIDTH_UNKNOWN;
++}
++EXPORT_SYMBOL(pcie_get_width_cap);
++
++/**
+ * pcie_get_minimum_link - determine minimum link settings of a PCI device
+ * @dev: PCI device to query
+ * @speed: storage for minimum speed
+diff --git a/include/linux/pci.h b/include/linux/pci.h
+index 76a681f..907fafa 100755
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -264,9 +264,13 @@ enum pci_bus_speed {
+ PCIE_SPEED_2_5GT = 0x14,
+ PCIE_SPEED_5_0GT = 0x15,
+ PCIE_SPEED_8_0GT = 0x16,
++ PCIE_SPEED_16_0GT = 0x17,
+ PCI_SPEED_UNKNOWN = 0xff,
+ };
+
++enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
++enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
++
+ struct pci_cap_saved_data {
+ u16 cap_nr;
+ bool cap_extended;
+diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
+index 009a432..fe1a8c9 100755
+--- a/include/uapi/linux/pci_regs.h
++++ b/include/uapi/linux/pci_regs.h
+@@ -520,6 +520,7 @@
+ #define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
+ #define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
+ #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
++#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */
+ #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
+ #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
+ #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
+@@ -649,6 +650,7 @@
+ #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 /* Supported Speed 2.5GT/s */
+ #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5.0GT/s */
+ #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8.0GT/s */
++#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
+ #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
+ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
+ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-19 08:13:24 +0000