1 files changed, 169 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4845-drm-amd-pp-Refine-the-interface-exported-to-display.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4845-drm-amd-pp-Refine-the-interface-exported-to-display.patch
new file mode 100644
index 00000000..42ed8bc7
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4845-drm-amd-pp-Refine-the-interface-exported-to-display.patch
@@ -0,0 +1,169 @@
+From d26360e4a01d8b74a5e220f714c4747766b7d763 Mon Sep 17 00:00:00 2001
+From: Rex Zhu <Rex.Zhu@amd.com>
+Date: Fri, 22 Jun 2018 18:26:52 +0800
+Subject: [PATCH 4845/5725] drm/amd/pp: Refine the interface exported to
+ display
+
+use void * as function parameter type in order for extension.
+
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/include/kgd_pp_interface.h        | 3 +--
+ drivers/gpu/drm/amd/powerplay/amd_powerplay.c         | 6 +++---
+ drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 4 ++--
+ drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c     | 3 ++-
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c    | 3 ++-
+ drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c    | 3 ++-
+ drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h   | 2 +-
+ drivers/gpu/drm/amd/powerplay/inc/hwmgr.h             | 3 +--
+ 8 files changed, 14 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+index 4535756..99ee3ed 100644
+--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+@@ -192,7 +192,6 @@ struct amd_pp_simple_clock_info;
+ struct amd_pp_display_configuration;
+ struct amd_pp_clock_info;
+ struct pp_display_clock_request;
+-struct pp_wm_sets_with_clock_ranges_soc15;
+ struct pp_clock_levels_with_voltage;
+ struct pp_clock_levels_with_latency;
+ struct amd_pp_clocks;
+@@ -261,7 +260,7 @@ struct amd_pm_funcs {
+ 		enum amd_pp_clock_type type,
+ 		struct pp_clock_levels_with_voltage *clocks);
+ 	int (*set_watermarks_for_clocks_ranges)(void *handle,
+-		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
++						void *clock_ranges);
+ 	int (*display_clock_voltage_request)(void *handle,
+ 				struct pp_display_clock_request *clock);
+ 	int (*get_display_mode_validation_clocks)(void *handle,
+diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+index 9e54bbe..68c19d4 100644
+--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
++++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+@@ -1106,17 +1106,17 @@ static int pp_get_clock_by_type_with_voltage(void *handle,
+ }
+ 
+ static int pp_set_watermarks_for_clocks_ranges(void *handle,
+-		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
++		void *clock_ranges)
+ {
+ 	struct pp_hwmgr *hwmgr = handle;
+ 	int ret = 0;
+ 
+-	if (!hwmgr || !hwmgr->pm_en ||!wm_with_clock_ranges)
++	if (!hwmgr || !hwmgr->pm_en || !clock_ranges)
+ 		return -EINVAL;
+ 
+ 	mutex_lock(&hwmgr->smu_lock);
+ 	ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
+-			wm_with_clock_ranges);
++			clock_ranges);
+ 	mutex_unlock(&hwmgr->smu_lock);
+ 
+ 	return ret;
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+index a0bb921..53207e7 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+@@ -435,7 +435,7 @@ int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
+ }
+ 
+ int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
+-		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
++					void *clock_ranges)
+ {
+ 	PHM_FUNC_CHECK(hwmgr);
+ 
+@@ -443,7 +443,7 @@ int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
+ 		return -EINVAL;
+ 
+ 	return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr,
+-			wm_with_clock_ranges);
++								clock_ranges);
+ }
+ 
+ int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+index 07cc98c..02fc0bc 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+@@ -1108,9 +1108,10 @@ static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
+ }
+ 
+ static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
+-		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
++		void *clock_ranges)
+ {
+ 	struct smu10_hwmgr *data = hwmgr->backend;
++	struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
+ 	Watermarks_t *table = &(data->water_marks_table);
+ 	int result = 0;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+index 5f00760..064b4467 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+@@ -4211,9 +4211,10 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
+ }
+ 
+ static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
+-		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
++							void *clock_range)
+ {
+ 	struct vega10_hwmgr *data = hwmgr->backend;
++	struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range;
+ 	Watermarks_t *table = &(data->smc_state_table.water_marks_table);
+ 	int result = 0;
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+index 4cf2570..448014b 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+@@ -1781,10 +1781,11 @@ static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
+ }
+ 
+ static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
+-		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
++							void *clock_ranges)
+ {
+ 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
+ 	Watermarks_t *table = &(data->smc_state_table.water_marks_table);
++	struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
+ 	uint32_t i;
+ 
+ 	if (!data->registry_data.disable_water_mark &&
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+index a202247..429c9c4 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+@@ -455,7 +455,7 @@ extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
+ 		enum amd_pp_clock_type type,
+ 		struct pp_clock_levels_with_voltage *clocks);
+ extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
+-		struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
++						void *clock_ranges);
+ extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
+ 		struct pp_display_clock_request *clock);
+ 
+diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+index 95e29a2..b3363f2 100644
+--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+@@ -293,8 +293,7 @@ struct pp_hwmgr_func {
+ 	int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
+ 			enum amd_pp_clock_type type,
+ 			struct pp_clock_levels_with_voltage *clocks);
+-	int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr,
+-			struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
++	int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
+ 	int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
+ 			struct pp_display_clock_request *clock);
+ 	int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
+-- 
+2.7.4
+