diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4746-drm-amdgpu-update-ib_start-size_alignment-same-as-wi.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4746-drm-amdgpu-update-ib_start-size_alignment-same-as-wi.patch | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4746-drm-amdgpu-update-ib_start-size_alignment-same-as-wi.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4746-drm-amdgpu-update-ib_start-size_alignment-same-as-wi.patch new file mode 100644 index 00000000..bbfe252b --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4746-drm-amdgpu-update-ib_start-size_alignment-same-as-wi.patch @@ -0,0 +1,105 @@ +From 62ca868522f57a526d3b6c4b99c18270ec397832 Mon Sep 17 00:00:00 2001 +From: Chunming Zhou <david1.zhou@amd.com> +Date: Fri, 15 Jun 2018 14:39:57 +0800 +Subject: [PATCH 4746/5725] drm/amdgpu: update ib_start/size_alignment same as + windows used +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +PAGE_SIZE for start_alignment is far much than hw requirement, +And now, update to expereince value from window side. + +Signed-off-by: Chunming Zhou <david1.zhou@amd.com> +Acked-by: Marek Olšák <marek.olsak@amd.com> +Acked-by: Christian König <christian.koenig@amd.com> +Acked-by: Junwei Zhang <Jerry.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 28 ++++++++++++++-------------- + 1 file changed, 14 insertions(+), 14 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +index a1a53c6..a7a0be9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +@@ -343,35 +343,35 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file + type = AMD_IP_BLOCK_TYPE_GFX; + for (i = 0; i < adev->gfx.num_gfx_rings; i++) + ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); +- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; +- ib_size_alignment = 8; ++ ib_start_alignment = 32; ++ ib_size_alignment = 32; + break; + case AMDGPU_HW_IP_COMPUTE: + type = AMD_IP_BLOCK_TYPE_GFX; + for (i = 0; i < adev->gfx.num_compute_rings; i++) + ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); +- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; +- ib_size_alignment = 8; ++ ib_start_alignment = 32; ++ ib_size_alignment = 32; + break; + case AMDGPU_HW_IP_DMA: + type = AMD_IP_BLOCK_TYPE_SDMA; + for (i = 0; i < adev->sdma.num_instances; i++) + ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); +- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; +- ib_size_alignment = 1; ++ ib_start_alignment = 256; ++ ib_size_alignment = 4; + break; + case AMDGPU_HW_IP_UVD: + type = AMD_IP_BLOCK_TYPE_UVD; + for (i = 0; i < adev->uvd.num_uvd_inst; i++) + ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1 : 0) << i); +- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; +- ib_size_alignment = 16; ++ ib_start_alignment = 64; ++ ib_size_alignment = 64; + break; + case AMDGPU_HW_IP_VCE: + type = AMD_IP_BLOCK_TYPE_VCE; + for (i = 0; i < adev->vce.num_rings; i++) + ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); +- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; ++ ib_start_alignment = 4; + ib_size_alignment = 1; + break; + case AMDGPU_HW_IP_UVD_ENC: +@@ -381,26 +381,26 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file + ring_mask |= + ((adev->uvd.inst[i].ring_enc[j].ready ? 1 : 0) << + (j + i * adev->uvd.num_enc_rings)); +- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; +- ib_size_alignment = 1; ++ ib_start_alignment = 64; ++ ib_size_alignment = 64; + break; + case AMDGPU_HW_IP_VCN_DEC: + type = AMD_IP_BLOCK_TYPE_VCN; + ring_mask = adev->vcn.ring_dec.ready ? 1 : 0; +- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; ++ ib_start_alignment = 16; + ib_size_alignment = 16; + break; + case AMDGPU_HW_IP_VCN_ENC: + type = AMD_IP_BLOCK_TYPE_VCN; + for (i = 0; i < adev->vcn.num_enc_rings; i++) + ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i); +- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; ++ ib_start_alignment = 64; + ib_size_alignment = 1; + break; + case AMDGPU_HW_IP_VCN_JPEG: + type = AMD_IP_BLOCK_TYPE_VCN; + ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0; +- ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; ++ ib_start_alignment = 16; + ib_size_alignment = 16; + break; + default: +-- +2.7.4 + |