diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4666-drm-amdgpu-gfx9-Update-golden-settings-for-vg10.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4666-drm-amdgpu-gfx9-Update-golden-settings-for-vg10.patch | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4666-drm-amdgpu-gfx9-Update-golden-settings-for-vg10.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4666-drm-amdgpu-gfx9-Update-golden-settings-for-vg10.patch new file mode 100644 index 00000000..e51e1069 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4666-drm-amdgpu-gfx9-Update-golden-settings-for-vg10.patch @@ -0,0 +1,45 @@ +From 82f35afbb3d32a9f5a42a0d292b6c03db3634927 Mon Sep 17 00:00:00 2001 +From: Feifei Xu <Feifei.Xu@amd.com> +Date: Tue, 17 Jul 2018 14:54:23 +0800 +Subject: [PATCH 4666/5725] drm/amdgpu/gfx9: Update golden settings for vg10. + +Add some UTCL registers' goldensettings. + +Change-Id: I1aea720d4527604baf68bf82d432d93f35dd0cd4 +Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> +Tested-by: Kevin Wang <Kevin1.Wang@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 ++++++++++++- + 1 file changed, 12 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 4527150..7a881ef 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -102,11 +102,22 @@ static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = + { + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000), +- SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800) ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080) + }; + + static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = +-- +2.7.4 + |