diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4643-drm-amd-include-Update-df-3.6-mask-and-shift-definit.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4643-drm-amd-include-Update-df-3.6-mask-and-shift-definit.patch | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4643-drm-amd-include-Update-df-3.6-mask-and-shift-definit.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4643-drm-amd-include-Update-df-3.6-mask-and-shift-definit.patch new file mode 100644 index 00000000..b53565d5 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4643-drm-amd-include-Update-df-3.6-mask-and-shift-definit.patch @@ -0,0 +1,40 @@ +From 4b7fdbcbd36dd6e3ec05da2f17186e674cc816ec Mon Sep 17 00:00:00 2001 +From: Shaoyun Liu <Shaoyun.Liu@amd.com> +Date: Tue, 12 Jun 2018 13:35:44 -0400 +Subject: [PATCH 4643/5725] drm/amd/include: Update df 3.6 mask and shift + definition + +The register field hsas been changed in df 3.6, update to correct setting + +Change-Id: Id625d7698b610c07081f421537964686f8f0b67c +Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h +index 88f7c69..06fac50 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h +@@ -36,13 +36,13 @@ + /* DF_CS_AON0_DramBaseAddress0 */ + #define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 + #define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 +-#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4 +-#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8 ++#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x2 ++#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x9 + #define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc + #define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L + #define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L +-#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L +-#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L ++#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x0000003CL ++#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000E00L + #define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L + + #endif +-- +2.7.4 + |