diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4635-drm-amdgpu-Added-ISR-for-CP-ECC-EDC-interrupt-v2.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4635-drm-amdgpu-Added-ISR-for-CP-ECC-EDC-interrupt-v2.patch | 165 |
1 files changed, 165 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4635-drm-amdgpu-Added-ISR-for-CP-ECC-EDC-interrupt-v2.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4635-drm-amdgpu-Added-ISR-for-CP-ECC-EDC-interrupt-v2.patch new file mode 100644 index 00000000..7b8d7a1d --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4635-drm-amdgpu-Added-ISR-for-CP-ECC-EDC-interrupt-v2.patch @@ -0,0 +1,165 @@ +From 72b12e47e86a563761cfb11bb0255b3bd712ffa1 Mon Sep 17 00:00:00 2001 +From: David Panariti <David.Panariti@amd.com> +Date: Tue, 15 May 2018 11:45:11 -0400 +Subject: [PATCH 4635/5725] drm/amdgpu: Added ISR for CP ECC/EDC interrupt v2. +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +ISR will DRM_ERROR ECC error message. + +v2: +Remove CZ only limitation. +Rebase. + +Signed-off-by: David Panariti <David.Panariti@amd.com> +Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> +Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 75 +++++++++++++++++++++++++++++++++++ + 2 files changed, 76 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index 89572c1..0571196 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -988,6 +988,7 @@ struct amdgpu_gfx { + struct amdgpu_irq_src eop_irq; + struct amdgpu_irq_src priv_reg_irq; + struct amdgpu_irq_src priv_inst_irq; ++ struct amdgpu_irq_src cp_ecc_error_irq; + /* gfx status */ + uint32_t gfx_current_status; + /* ce ram size*/ +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 1ad8528..b92abc3 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -2055,6 +2055,12 @@ static int gfx_v8_0_sw_init(void *handle) + if (r) + return r; + ++ /* Add CP EDC/ECC irq */ ++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 197, ++ &adev->gfx.cp_ecc_error_irq); ++ if (r) ++ return r; ++ + adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; + + gfx_v8_0_scratch_init(adev); +@@ -5118,6 +5124,8 @@ static int gfx_v8_0_hw_fini(void *handle) + amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); + ++ amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); ++ + /* disable KCQ to avoid CPC touch memory not valid anymore */ + for (i = 0; i < adev->gfx.num_compute_rings; i++) + gfx_v8_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]); +@@ -5549,6 +5557,12 @@ static int gfx_v8_0_late_init(void *handle) + if (r) + return r; + ++ r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); ++ if (r) { ++ DRM_ERROR("amdgpu_irq_get() failed to get IRQ for EDC, r: %d.\n", r); ++ return r; ++ } ++ + amdgpu_device_ip_set_powergating_state(adev, + AMD_IP_BLOCK_TYPE_GFX, + AMD_PG_STATE_GATE); +@@ -6807,6 +6821,51 @@ static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev, + return 0; + } + ++static int gfx_v8_0_set_cp_ecc_int_state(struct amdgpu_device *adev, ++ struct amdgpu_irq_src *source, ++ unsigned int type, ++ enum amdgpu_interrupt_state state) ++{ ++ int enable_flag; ++ ++ switch (state) { ++ case AMDGPU_IRQ_STATE_DISABLE: ++ enable_flag = 0; ++ break; ++ ++ case AMDGPU_IRQ_STATE_ENABLE: ++ enable_flag = 1; ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ WREG32_FIELD(CP_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag); ++ WREG32_FIELD(CP_INT_CNTL_RING0, CP_ECC_ERROR_INT_ENABLE, enable_flag); ++ WREG32_FIELD(CP_INT_CNTL_RING1, CP_ECC_ERROR_INT_ENABLE, enable_flag); ++ WREG32_FIELD(CP_INT_CNTL_RING2, CP_ECC_ERROR_INT_ENABLE, enable_flag); ++ WREG32_FIELD(CPC_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, enable_flag); ++ WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, ++ enable_flag); ++ WREG32_FIELD(CP_ME1_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, ++ enable_flag); ++ WREG32_FIELD(CP_ME1_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, ++ enable_flag); ++ WREG32_FIELD(CP_ME1_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, ++ enable_flag); ++ WREG32_FIELD(CP_ME2_PIPE0_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, ++ enable_flag); ++ WREG32_FIELD(CP_ME2_PIPE1_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, ++ enable_flag); ++ WREG32_FIELD(CP_ME2_PIPE2_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, ++ enable_flag); ++ WREG32_FIELD(CP_ME2_PIPE3_INT_CNTL, CP_ECC_ERROR_INT_ENABLE, ++ enable_flag); ++ ++ return 0; ++} ++ + static int gfx_v8_0_eop_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +@@ -6857,6 +6916,14 @@ static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev, + return 0; + } + ++static int gfx_v8_0_cp_ecc_error_irq(struct amdgpu_device *adev, ++ struct amdgpu_irq_src *source, ++ struct amdgpu_iv_entry *entry) ++{ ++ DRM_ERROR("ECC error detected."); ++ return 0; ++} ++ + static int gfx_v8_0_kiq_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, +@@ -7059,6 +7126,11 @@ static const struct amdgpu_irq_src_funcs gfx_v8_0_kiq_irq_funcs = { + .process = gfx_v8_0_kiq_irq, + }; + ++static const struct amdgpu_irq_src_funcs gfx_v8_0_cp_ecc_error_irq_funcs = { ++ .set = gfx_v8_0_set_cp_ecc_int_state, ++ .process = gfx_v8_0_cp_ecc_error_irq, ++}; ++ + static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev) + { + adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; +@@ -7072,6 +7144,9 @@ static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev) + + adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; + adev->gfx.kiq.irq.funcs = &gfx_v8_0_kiq_irq_funcs; ++ ++ adev->gfx.cp_ecc_error_irq.num_types = 1; ++ adev->gfx.cp_ecc_error_irq.funcs = &gfx_v8_0_cp_ecc_error_irq_funcs; + } + + static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev) +-- +2.7.4 + |