diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4601-drm-amdgpu-add-more-jpeg-register-offset-headers.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4601-drm-amdgpu-add-more-jpeg-register-offset-headers.patch | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4601-drm-amdgpu-add-more-jpeg-register-offset-headers.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4601-drm-amdgpu-add-more-jpeg-register-offset-headers.patch new file mode 100644 index 00000000..de218936 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4601-drm-amdgpu-add-more-jpeg-register-offset-headers.patch @@ -0,0 +1,71 @@ +From 250d38b4e02a461e04fbda1558bb8ff8cc6691df Mon Sep 17 00:00:00 2001 +From: Boyuan Zhang <boyuan.zhang@amd.com> +Date: Mon, 30 Apr 2018 16:55:39 -0400 +Subject: [PATCH 4601/5725] drm/amdgpu: add more jpeg register offset headers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add more jpeg registers defines that are needed for jpeg ring functions + +Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> +Reviewed-by: Christian König <christian.koenig@amd.com> +--- + .../drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h +index 18a3247..fe0cbaa 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h +@@ -89,6 +89,8 @@ + #define mmUVD_JPEG_RB_SIZE_BASE_IDX 1 + #define mmUVD_JPEG_ADDR_CONFIG 0x021f + #define mmUVD_JPEG_ADDR_CONFIG_BASE_IDX 1 ++#define mmUVD_JPEG_PITCH 0x0222 ++#define mmUVD_JPEG_PITCH_BASE_IDX 1 + #define mmUVD_JPEG_GPCOM_CMD 0x022c + #define mmUVD_JPEG_GPCOM_CMD_BASE_IDX 1 + #define mmUVD_JPEG_GPCOM_DATA0 0x022d +@@ -203,6 +205,8 @@ + #define mmUVD_RB_WPTR4_BASE_IDX 1 + #define mmUVD_JRBC_RB_RPTR 0x0457 + #define mmUVD_JRBC_RB_RPTR_BASE_IDX 1 ++#define mmUVD_LMI_JPEG_VMID 0x045d ++#define mmUVD_LMI_JPEG_VMID_BASE_IDX 1 + #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x045e + #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH_BASE_IDX 1 + #define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x045f +@@ -231,6 +235,8 @@ + #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_BASE_IDX 1 + #define mmUVD_LMI_JRBC_IB_VMID 0x0507 + #define mmUVD_LMI_JRBC_IB_VMID_BASE_IDX 1 ++#define mmUVD_LMI_JRBC_RB_VMID 0x0508 ++#define mmUVD_LMI_JRBC_RB_VMID_BASE_IDX 1 + #define mmUVD_JRBC_RB_WPTR 0x0509 + #define mmUVD_JRBC_RB_WPTR_BASE_IDX 1 + #define mmUVD_JRBC_RB_CNTL 0x050a +@@ -239,6 +245,20 @@ + #define mmUVD_JRBC_IB_SIZE_BASE_IDX 1 + #define mmUVD_JRBC_LMI_SWAP_CNTL 0x050d + #define mmUVD_JRBC_LMI_SWAP_CNTL_BASE_IDX 1 ++#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 0x050e ++#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_BASE_IDX 1 ++#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 0x050f ++#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_BASE_IDX 1 ++#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 0x0510 ++#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_BASE_IDX 1 ++#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 0x0511 ++#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_BASE_IDX 1 ++#define mmUVD_JRBC_RB_REF_DATA 0x0512 ++#define mmUVD_JRBC_RB_REF_DATA_BASE_IDX 1 ++#define mmUVD_JRBC_RB_COND_RD_TIMER 0x0513 ++#define mmUVD_JRBC_RB_COND_RD_TIMER_BASE_IDX 1 ++#define mmUVD_JRBC_EXTERNAL_REG_BASE 0x0517 ++#define mmUVD_JRBC_EXTERNAL_REG_BASE_BASE_IDX 1 + #define mmUVD_JRBC_SOFT_RESET 0x0519 + #define mmUVD_JRBC_SOFT_RESET_BASE_IDX 1 + #define mmUVD_JRBC_STATUS 0x051a +-- +2.7.4 + |