diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4497-drm-amd-pp-Add-smu-support-for-VCN-powergating-on-RV.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4497-drm-amd-pp-Add-smu-support-for-VCN-powergating-on-RV.patch | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4497-drm-amd-pp-Add-smu-support-for-VCN-powergating-on-RV.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4497-drm-amd-pp-Add-smu-support-for-VCN-powergating-on-RV.patch new file mode 100644 index 00000000..2a2a3354 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4497-drm-amd-pp-Add-smu-support-for-VCN-powergating-on-RV.patch @@ -0,0 +1,53 @@ +From e10dda05e76a3045dfa93cee7a33da8739693912 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Wed, 16 May 2018 20:09:09 +0800 +Subject: [PATCH 4497/5725] drm/amd/pp: Add smu support for VCN powergating on + RV + +Change-Id: I56283fa94c7bf3778a988369f18f83648ea2a55d +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 19 ++++++++++++++++++- + 1 file changed, 18 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +index fdb0282..2df791c 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +@@ -1128,6 +1128,23 @@ static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr) + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub); + } + ++static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate) ++{ ++ if (bgate) { ++ amdgpu_device_ip_set_powergating_state(hwmgr->adev, ++ AMD_IP_BLOCK_TYPE_VCN, ++ AMD_PG_STATE_GATE); ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_PowerDownVcn, 0); ++ } else { ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_PowerUpVcn, 0); ++ amdgpu_device_ip_set_powergating_state(hwmgr->adev, ++ AMD_IP_BLOCK_TYPE_VCN, ++ AMD_PG_STATE_UNGATE); ++ } ++} ++ + static const struct pp_hwmgr_func smu10_hwmgr_funcs = { + .backend_init = smu10_hwmgr_backend_init, + .backend_fini = smu10_hwmgr_backend_fini, +@@ -1136,7 +1153,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = { + .force_dpm_level = smu10_dpm_force_dpm_level, + .get_power_state_size = smu10_get_power_state_size, + .powerdown_uvd = NULL, +- .powergate_uvd = NULL, ++ .powergate_uvd = smu10_powergate_vcn, + .powergate_vce = NULL, + .get_mclk = smu10_dpm_get_mclk, + .get_sclk = smu10_dpm_get_sclk, +-- +2.7.4 + |