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-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/4439-drm-amdgpu-df-implement-df-v3_6-callback-functions-v.patch207
1 files changed, 207 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4439-drm-amdgpu-df-implement-df-v3_6-callback-functions-v.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4439-drm-amdgpu-df-implement-df-v3_6-callback-functions-v.patch
new file mode 100644
index 00000000..5e894d03
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4439-drm-amdgpu-df-implement-df-v3_6-callback-functions-v.patch
@@ -0,0 +1,207 @@
+From 09a0d883ca7a3d39b7aebfa67ba8ff0a59f9b291 Mon Sep 17 00:00:00 2001
+From: Feifei Xu <Feifei.Xu@amd.com>
+Date: Wed, 4 Apr 2018 14:30:28 +0800
+Subject: [PATCH 4439/5725] drm/amdgpu/df: implement df v3_6 callback functions
+ (v2)
+
+New df helpers for 3.6.
+
+v2: switch to using df 3.6 headers (Alex)
+
+Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Reviewed-by: Huang Rui <ray.huang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/Makefile | 3 +-
+ drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 116 +++++++++++++++++++++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/df_v3_6.h | 40 ++++++++++++
+ 3 files changed, 158 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/df_v3_6.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
+index 53b246a..b16581d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/Makefile
++++ b/drivers/gpu/drm/amd/amdgpu/Makefile
+@@ -46,7 +46,8 @@ amdgpu-y += \
+
+ # add DF block
+ amdgpu-y += \
+- df_v1_7.o
++ df_v1_7.o \
++ df_v3_6.o
+
+ # add GMC block
+ amdgpu-y += \
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+new file mode 100644
+index 0000000..60608b3
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
+@@ -0,0 +1,116 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++#include "amdgpu.h"
++#include "df_v3_6.h"
++
++#include "df/df_3_6_default.h"
++#include "df/df_3_6_offset.h"
++#include "df/df_3_6_sh_mask.h"
++
++static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,
++ 16, 32, 0, 0, 0, 2, 4, 8};
++
++static void df_v3_6_init(struct amdgpu_device *adev)
++{
++}
++
++static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev,
++ bool enable)
++{
++ u32 tmp;
++
++ if (enable) {
++ tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
++ tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
++ WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
++ } else
++ WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
++ mmFabricConfigAccessControl_DEFAULT);
++}
++
++static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev)
++{
++ u32 tmp;
++
++ tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
++ tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
++ tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
++
++ return tmp;
++}
++
++static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev)
++{
++ int fb_channel_number;
++
++ fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
++ if (fb_channel_number > ARRAY_SIZE(df_v3_6_channel_number))
++ fb_channel_number = 0;
++
++ return df_v3_6_channel_number[fb_channel_number];
++}
++
++static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
++ bool enable)
++{
++ u32 tmp;
++
++ /* Put DF on broadcast mode */
++ adev->df_funcs->enable_broadcast_mode(adev, true);
++
++ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
++ tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
++ tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
++ tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
++ WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
++ } else {
++ tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
++ tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
++ tmp |= DF_V3_6_MGCG_DISABLE;
++ WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
++ }
++
++ /* Exit broadcast mode */
++ adev->df_funcs->enable_broadcast_mode(adev, false);
++}
++
++static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
++ u32 *flags)
++{
++ u32 tmp;
++
++ /* AMD_CG_SUPPORT_DF_MGCG */
++ tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
++ if (tmp & DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY)
++ *flags |= AMD_CG_SUPPORT_DF_MGCG;
++}
++
++const struct amdgpu_df_funcs df_v3_6_funcs = {
++ .init = df_v3_6_init,
++ .enable_broadcast_mode = df_v3_6_enable_broadcast_mode,
++ .get_fb_channel_number = df_v3_6_get_fb_channel_number,
++ .get_hbm_channel_number = df_v3_6_get_hbm_channel_number,
++ .update_medium_grain_clock_gating =
++ df_v3_6_update_medium_grain_clock_gating,
++ .get_clockgating_state = df_v3_6_get_clockgating_state,
++};
+diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.h b/drivers/gpu/drm/amd/amdgpu/df_v3_6.h
+new file mode 100644
+index 0000000..e79c58e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.h
+@@ -0,0 +1,40 @@
++/*
++ * Copyright 2018 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included in
++ * all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ * OTHER DEALINGS IN THE SOFTWARE.
++ *
++ */
++
++#ifndef __DF_V3_6_H__
++#define __DF_V3_6_H__
++
++#include "soc15_common.h"
++
++enum DF_V3_6_MGCG {
++ DF_V3_6_MGCG_DISABLE = 0,
++ DF_V3_6_MGCG_ENABLE_00_CYCLE_DELAY = 1,
++ DF_V3_6_MGCG_ENABLE_01_CYCLE_DELAY = 2,
++ DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY = 13,
++ DF_V3_6_MGCG_ENABLE_31_CYCLE_DELAY = 14,
++ DF_V3_6_MGCG_ENABLE_63_CYCLE_DELAY = 15
++};
++
++extern const struct amdgpu_df_funcs df_v3_6_funcs;
++
++#endif
+--
+2.7.4
+