diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4438-drm-amdgpu-add-df-3.6-headers.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4438-drm-amdgpu-add-df-3.6-headers.patch | 145 |
1 files changed, 145 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4438-drm-amdgpu-add-df-3.6-headers.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4438-drm-amdgpu-add-df-3.6-headers.patch new file mode 100644 index 00000000..41e9af4e --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4438-drm-amdgpu-add-df-3.6-headers.patch @@ -0,0 +1,145 @@ +From 718426b3a2a9b75466cf8c6242f1e730e32f9622 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Mon, 14 May 2018 11:50:46 -0500 +Subject: [PATCH 4438/5725] drm/amdgpu: add df 3.6 headers + +Needed for vega20. + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../drm/amd/include/asic_reg/df/df_3_6_default.h | 26 ++++++++++++ + .../drm/amd/include/asic_reg/df/df_3_6_offset.h | 33 +++++++++++++++ + .../drm/amd/include/asic_reg/df/df_3_6_sh_mask.h | 48 ++++++++++++++++++++++ + 3 files changed, 107 insertions(+) + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_default.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_default.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_default.h +new file mode 100644 +index 0000000..e58c207 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_default.h +@@ -0,0 +1,26 @@ ++/* ++ * Copyright (C) 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _df_3_6_DEFAULT_HEADER ++#define _df_3_6_DEFAULT_HEADER ++ ++#define mmFabricConfigAccessControl_DEFAULT 0x00000000 ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h +new file mode 100644 +index 0000000..a9575db +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_offset.h +@@ -0,0 +1,33 @@ ++/* ++ * Copyright (C) 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _df_3_6_OFFSET_HEADER ++#define _df_3_6_OFFSET_HEADER ++ ++#define mmFabricConfigAccessControl 0x0410 ++#define mmFabricConfigAccessControl_BASE_IDX 0 ++ ++#define mmDF_PIE_AON0_DfGlobalClkGater 0x00fc ++#define mmDF_PIE_AON0_DfGlobalClkGater_BASE_IDX 0 ++ ++#define mmDF_CS_UMC_AON0_DramBaseAddress0 0x0044 ++#define mmDF_CS_UMC_AON0_DramBaseAddress0_BASE_IDX 0 ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h +new file mode 100644 +index 0000000..88f7c69 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/df/df_3_6_sh_mask.h +@@ -0,0 +1,48 @@ ++/* ++ * Copyright (C) 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _df_3_6_SH_MASK_HEADER ++#define _df_3_6_SH_MASK_HEADER ++ ++/* FabricConfigAccessControl */ ++#define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0 ++#define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1 ++#define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10 ++#define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L ++#define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L ++#define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L ++ ++/* DF_PIE_AON0_DfGlobalClkGater */ ++#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0 ++#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL ++ ++/* DF_CS_AON0_DramBaseAddress0 */ ++#define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0 ++#define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1 ++#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x4 ++#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x8 ++#define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc ++#define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L ++#define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L ++#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x000000F0L ++#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000700L ++#define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L ++ ++#endif +-- +2.7.4 + |