diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4433-drm-amdgpu-vg20-Enable-the-2nd-instance-for-uvd.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4433-drm-amdgpu-vg20-Enable-the-2nd-instance-for-uvd.patch | 104 |
1 files changed, 104 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4433-drm-amdgpu-vg20-Enable-the-2nd-instance-for-uvd.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4433-drm-amdgpu-vg20-Enable-the-2nd-instance-for-uvd.patch new file mode 100644 index 00000000..6f14d5ce --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4433-drm-amdgpu-vg20-Enable-the-2nd-instance-for-uvd.patch @@ -0,0 +1,104 @@ +From bd96fc812b85409c88884902eb5845dee2e49bee Mon Sep 17 00:00:00 2001 +From: James Zhu <James.Zhu@amd.com> +Date: Fri, 11 May 2018 13:56:44 -0500 +Subject: [PATCH 4433/5725] drm/amdgpu/vg20:Enable the 2nd instance for uvd + +For Vega20, set num of uvd instance to 2, to enble 2nd instance. +The IB test build-in registers need update for vega20 2nd instance. + +Signed-off-by: James Zhu <James.Zhu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Kalyan Alle <kalyan.alle@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 32 +++++++++++++++++--------------- + drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 7 ++++++- + 2 files changed, 23 insertions(+), 16 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +index 3c040f3..c973b10 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +@@ -72,11 +72,12 @@ + #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" + #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin" + +-#define mmUVD_GPCOM_VCPU_DATA0_VEGA10 (0x03c4 + 0x7e00) +-#define mmUVD_GPCOM_VCPU_DATA1_VEGA10 (0x03c5 + 0x7e00) +-#define mmUVD_GPCOM_VCPU_CMD_VEGA10 (0x03c3 + 0x7e00) +-#define mmUVD_NO_OP_VEGA10 (0x03ff + 0x7e00) +-#define mmUVD_ENGINE_CNTL_VEGA10 (0x03c6 + 0x7e00) ++/* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ ++#define UVD_GPCOM_VCPU_CMD 0x03c3 ++#define UVD_GPCOM_VCPU_DATA0 0x03c4 ++#define UVD_GPCOM_VCPU_DATA1 0x03c5 ++#define UVD_NO_OP 0x03ff ++#define UVD_BASE_SI 0x3800 + + /** + * amdgpu_uvd_cs_ctx - Command submission parser context +@@ -990,7 +991,9 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, + uint64_t addr; + long r; + int i; +- ++ unsigned offset_idx = 0; ++ unsigned offset[3] = { UVD_BASE_SI, 0, 0 }; ++ + amdgpu_bo_kunmap(bo); + amdgpu_bo_unpin(bo); + +@@ -1009,17 +1012,16 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, + goto err; + + if (adev->asic_type >= CHIP_VEGA10) { +- data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0); +- data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0); +- data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0); +- data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0); +- } else { +- data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0); +- data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0); +- data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0); +- data[3] = PACKET0(mmUVD_NO_OP, 0); ++ offset_idx = 1 + ring->me; ++ offset[1] = adev->reg_offset[UVD_HWIP][0][1]; ++ offset[2] = adev->reg_offset[UVD_HWIP][1][1]; + } + ++ data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0); ++ data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0); ++ data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0); ++ data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0); ++ + ib = &job->ibs[0]; + addr = amdgpu_bo_gpu_offset(bo); + ib->ptr[0] = data[0]; +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +index 38816227..bc4db67 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +@@ -40,6 +40,8 @@ + #include "mmhub/mmhub_1_0_offset.h" + #include "mmhub/mmhub_1_0_sh_mask.h" + ++#define UVD7_MAX_HW_INSTANCES_VEGA20 2 ++ + static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev); + static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev); + static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev); +@@ -370,7 +372,10 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) + static int uvd_v7_0_early_init(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; +- adev->uvd.num_uvd_inst = 1; ++ if (adev->asic_type == CHIP_VEGA20) ++ adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20; ++ else ++ adev->uvd.num_uvd_inst = 1; + + if (amdgpu_sriov_vf(adev)) + adev->uvd.num_enc_rings = 1; +-- +2.7.4 + |