diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4409-drm-amdgpu-soc15-dynamic-initialize-ip-offset-for-ve.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4409-drm-amdgpu-soc15-dynamic-initialize-ip-offset-for-ve.patch | 122 |
1 files changed, 122 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4409-drm-amdgpu-soc15-dynamic-initialize-ip-offset-for-ve.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4409-drm-amdgpu-soc15-dynamic-initialize-ip-offset-for-ve.patch new file mode 100644 index 00000000..f83d1293 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4409-drm-amdgpu-soc15-dynamic-initialize-ip-offset-for-ve.patch @@ -0,0 +1,122 @@ +From aa0f9d4161502946d3813537cfabde0e26722b48 Mon Sep 17 00:00:00 2001 +From: Feifei Xu <Feifei.Xu@amd.com> +Date: Fri, 23 Mar 2018 14:42:28 -0500 +Subject: [PATCH 4409/5725] drm/amdgpu/soc15: dynamic initialize ip offset for + vega20 + +Vega20 need a seperate vega20_reg_init.c due to ip base +offset difference. + +Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- + drivers/gpu/drm/amd/amdgpu/soc15.c | 3 ++ + drivers/gpu/drm/amd/amdgpu/soc15.h | 1 + + drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c | 53 ++++++++++++++++++++++++++++ + 4 files changed, 59 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c + +diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile +index 4a558d6..53b246a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/Makefile ++++ b/drivers/gpu/drm/amd/amdgpu/Makefile +@@ -41,7 +41,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ + amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o + + amdgpu-y += \ +- vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o ++ vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \ ++ vega20_reg_init.o + + # add DF block + amdgpu-y += \ +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index 1fd75f5..c3133d1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -487,6 +487,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) + case CHIP_RAVEN: + vega10_reg_base_init(adev); + break; ++ case CHIP_VEGA20: ++ vega20_reg_base_init(adev); ++ break; + default: + return -EINVAL; + } +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h +index f70da8a..1f714b7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.h ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.h +@@ -55,5 +55,6 @@ void soc15_program_register_sequence(struct amdgpu_device *adev, + const u32 array_size); + + int vega10_reg_base_init(struct amdgpu_device *adev); ++int vega20_reg_base_init(struct amdgpu_device *adev); + + #endif +diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c +new file mode 100644 +index 0000000..52778de +--- /dev/null ++++ b/drivers/gpu/drm/amd/amdgpu/vega20_reg_init.c +@@ -0,0 +1,53 @@ ++/* ++ * Copyright 2018 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#include "amdgpu.h" ++#include "soc15.h" ++ ++#include "soc15_common.h" ++#include "soc15_hw_ip.h" ++#include "vega20_ip_offset.h" ++ ++int vega20_reg_base_init(struct amdgpu_device *adev) ++{ ++ /* HW has more IP blocks, only initialized the blocke beend by our driver */ ++ uint32_t i; ++ for (i = 0 ; i < MAX_INSTANCE ; ++i) { ++ adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); ++ adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); ++ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); ++ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); ++ adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); ++ adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); ++ adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); ++ adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); ++ adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); ++ adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i])); ++ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); ++ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); ++ adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); ++ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); ++ } ++ return 0; ++} ++ ++ +-- +2.7.4 + |