diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4404-drm-amdgpu-gfx9-Add-gfx-config-for-vega20.-v3.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4404-drm-amdgpu-gfx9-Add-gfx-config-for-vega20.-v3.patch | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4404-drm-amdgpu-gfx9-Add-gfx-config-for-vega20.-v3.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4404-drm-amdgpu-gfx9-Add-gfx-config-for-vega20.-v3.patch new file mode 100644 index 00000000..5fd9bc7e --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4404-drm-amdgpu-gfx9-Add-gfx-config-for-vega20.-v3.patch @@ -0,0 +1,41 @@ +From 66a475ed75c98aa5d5cabc8bc1ed913abd206eee Mon Sep 17 00:00:00 2001 +From: Feifei Xu <Feifei.Xu@amd.com> +Date: Fri, 20 Apr 2018 14:40:11 +0800 +Subject: [PATCH 4404/5725] drm/amdgpu/gfx9: Add gfx config for vega20. (v3) + +v2: clean up (Alex) +v3: additional cleanups (Alex) + +Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 2019170..5c9e44f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -1137,6 +1137,17 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) + gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN; + DRM_INFO("fix gfx.config for vega12\n"); + break; ++ case CHIP_VEGA20: ++ adev->gfx.config.max_hw_contexts = 8; ++ adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; ++ adev->gfx.config.sc_prim_fifo_size_backend = 0x100; ++ adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; ++ adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; ++ //TODO: Need to update this for vega20 ++ gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); ++ gb_addr_config &= ~0xf3e777ff; ++ gb_addr_config |= 0x22014042; ++ break; + case CHIP_RAVEN: + adev->gfx.config.max_hw_contexts = 8; + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; +-- +2.7.4 + |