diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4403-drm-amdgpu-gfx9-Add-vega20-golden-settings-v3.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4403-drm-amdgpu-gfx9-Add-vega20-golden-settings-v3.patch | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4403-drm-amdgpu-gfx9-Add-vega20-golden-settings-v3.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4403-drm-amdgpu-gfx9-Add-vega20-golden-settings-v3.patch new file mode 100644 index 00000000..4b2fb4ea --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4403-drm-amdgpu-gfx9-Add-vega20-golden-settings-v3.patch @@ -0,0 +1,59 @@ +From 0db85cf51654aae688974fae4bce958db6d477e3 Mon Sep 17 00:00:00 2001 +From: Feifei Xu <Feifei.Xu@amd.com> +Date: Tue, 23 Jan 2018 14:47:26 +0800 +Subject: [PATCH 4403/5725] drm/amdgpu/gfx9: Add vega20 golden settings (v3) + +v2: squash in updates (Alex) +v3: squash in more updates (Alex) + +Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 47ab06a..2019170 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -108,6 +108,20 @@ static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] = + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800) + }; + ++static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] = ++{ ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000) ++}; ++ + static const struct soc15_reg_golden golden_settings_gc_9_1[] = + { + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104), +@@ -241,6 +255,14 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) + golden_settings_gc_9_2_1_vg12, + ARRAY_SIZE(golden_settings_gc_9_2_1_vg12)); + break; ++ case CHIP_VEGA20: ++ soc15_program_register_sequence(adev, ++ golden_settings_gc_9_0, ++ ARRAY_SIZE(golden_settings_gc_9_0)); ++ soc15_program_register_sequence(adev, ++ golden_settings_gc_9_0_vg20, ++ ARRAY_SIZE(golden_settings_gc_9_0_vg20)); ++ break; + case CHIP_RAVEN: + soc15_program_register_sequence(adev, + golden_settings_gc_9_1, +-- +2.7.4 + |