diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4382-drm-amd-powerplay-new-framework-to-honour-DAL-clock-.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4382-drm-amd-powerplay-new-framework-to-honour-DAL-clock-.patch | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4382-drm-amd-powerplay-new-framework-to-honour-DAL-clock-.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4382-drm-amd-powerplay-new-framework-to-honour-DAL-clock-.patch new file mode 100644 index 00000000..72045dd7 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4382-drm-amd-powerplay-new-framework-to-honour-DAL-clock-.patch @@ -0,0 +1,87 @@ +From b22ad036507501190c9283aff6706bd9faa85daa Mon Sep 17 00:00:00 2001 +From: Evan Quan <evan.quan@amd.com> +Date: Wed, 9 May 2018 10:57:53 +0800 +Subject: [PATCH 4382/5725] drm/amd/powerplay: new framework to honour DAL + clock limits + +This is needed for vega12 and vega20 which do not support legacy +powerstate. With this new framework, the DAL clocks limits can also +be honored on these asics. + +Signed-off-by: Evan Quan <evan.quan@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 9 +++++++++ + drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c | 7 +++++++ + drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h | 2 ++ + drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 ++ + 4 files changed, 20 insertions(+) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c +index e411012..f5571e9f 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c +@@ -132,6 +132,15 @@ int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + return 0; + } + ++int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr) ++{ ++ PHM_FUNC_CHECK(hwmgr); ++ ++ if (hwmgr->hwmgr_func->apply_clocks_adjust_rules != NULL) ++ return hwmgr->hwmgr_func->apply_clocks_adjust_rules(hwmgr); ++ return 0; ++} ++ + int phm_powerdown_uvd(struct pp_hwmgr *hwmgr) + { + PHM_FUNC_CHECK(hwmgr); +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c +index 308bff2..2a2955c 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c +@@ -265,6 +265,13 @@ int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip, + if (skip) + return 0; + ++ if (!hwmgr->ps) ++ /* ++ * for vega12/vega20 which does not support power state manager ++ * DAL clock limits should also be honoured ++ */ ++ phm_apply_clock_adjust_rules(hwmgr); ++ + phm_display_configuration_changed(hwmgr); + + if (hwmgr->ps) +diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h +index 9bb8785..e029555 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h +@@ -410,6 +410,8 @@ extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + struct pp_power_state *adjusted_ps, + const struct pp_power_state *current_ps); + ++extern int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr); ++ + extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level); + extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr); + extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr); +diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +index 3c321c7..9b6c6af 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +@@ -229,6 +229,8 @@ struct pp_hwmgr_func { + struct pp_power_state *prequest_ps, + const struct pp_power_state *pcurrent_ps); + ++ int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr); ++ + int (*force_dpm_level)(struct pp_hwmgr *hw_mgr, + enum amd_dpm_forced_level level); + +-- +2.7.4 + |