diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4364-drm-amd-display-Add-get_firmware_info_v3_2-for-VG12.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4364-drm-amd-display-Add-get_firmware_info_v3_2-for-VG12.patch | 128 |
1 files changed, 128 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4364-drm-amd-display-Add-get_firmware_info_v3_2-for-VG12.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4364-drm-amd-display-Add-get_firmware_info_v3_2-for-VG12.patch new file mode 100644 index 00000000..5f4f325e --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4364-drm-amd-display-Add-get_firmware_info_v3_2-for-VG12.patch @@ -0,0 +1,128 @@ +From 7686f1f3937593e56f1a407f7f2270083a44d529 Mon Sep 17 00:00:00 2001 +From: Harry Wentland <harry.wentland@amd.com> +Date: Fri, 20 Apr 2018 10:56:18 -0400 +Subject: [PATCH 4364/5725] drm/amd/display: Add get_firmware_info_v3_2 for + VG12 + +Signed-off-by: Harry Wentland <harry.wentland@amd.com> +Acked-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 86 +++++++++++++++++++++- + 1 file changed, 85 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +index 985fe8c..10a5807 100644 +--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c ++++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +@@ -70,6 +70,10 @@ static enum bp_result get_firmware_info_v3_1( + struct bios_parser *bp, + struct dc_firmware_info *info); + ++static enum bp_result get_firmware_info_v3_2( ++ struct bios_parser *bp, ++ struct dc_firmware_info *info); ++ + static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp, + struct atom_display_object_path_v2 *object); + +@@ -1321,9 +1325,11 @@ static enum bp_result bios_parser_get_firmware_info( + case 3: + switch (revision.minor) { + case 1: +- case 2: + result = get_firmware_info_v3_1(bp, info); + break; ++ case 2: ++ result = get_firmware_info_v3_2(bp, info); ++ break; + default: + break; + } +@@ -1383,6 +1389,84 @@ static enum bp_result get_firmware_info_v3_1( + return BP_RESULT_OK; + } + ++static enum bp_result get_firmware_info_v3_2( ++ struct bios_parser *bp, ++ struct dc_firmware_info *info) ++{ ++ struct atom_firmware_info_v3_2 *firmware_info; ++ struct atom_display_controller_info_v4_1 *dce_info = NULL; ++ struct atom_common_table_header *header; ++ struct atom_data_revision revision; ++ struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL; ++ struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL; ++ ++ if (!info) ++ return BP_RESULT_BADINPUT; ++ ++ firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2, ++ DATA_TABLES(firmwareinfo)); ++ ++ dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1, ++ DATA_TABLES(dce_info)); ++ ++ if (!firmware_info || !dce_info) ++ return BP_RESULT_BADBIOSTABLE; ++ ++ memset(info, 0, sizeof(*info)); ++ ++ header = GET_IMAGE(struct atom_common_table_header, ++ DATA_TABLES(smu_info)); ++ get_atom_data_table_revision(header, &revision); ++ ++ if (revision.minor == 2) { ++ /* Vega12 */ ++ smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2, ++ DATA_TABLES(smu_info)); ++ ++ if (!smu_info_v3_2) ++ return BP_RESULT_BADBIOSTABLE; ++ ++ info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10; ++ } else if (revision.minor == 3) { ++ /* Vega20 */ ++ smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3, ++ DATA_TABLES(smu_info)); ++ ++ if (!smu_info_v3_3) ++ return BP_RESULT_BADBIOSTABLE; ++ ++ info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10; ++ } ++ ++ // We need to convert from 10KHz units into KHz units. ++ info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10; ++ ++ /* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */ ++ info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10; ++ /* Hardcode frequency if BIOS gives no DCE Ref Clk */ ++ if (info->pll_info.crystal_frequency == 0) { ++ if (revision.minor == 2) ++ info->pll_info.crystal_frequency = 27000; ++ else if (revision.minor == 3) ++ info->pll_info.crystal_frequency = 100000; ++ } ++ /*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/ ++ info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10; ++ info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10; ++ ++ /* Get GPU PLL VCO Clock */ ++ if (bp->cmd_tbl.get_smu_clock_info != NULL) { ++ if (revision.minor == 2) ++ info->smu_gpu_pll_output_freq = ++ bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10; ++ else if (revision.minor == 3) ++ info->smu_gpu_pll_output_freq = ++ bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10; ++ } ++ ++ return BP_RESULT_OK; ++} ++ + static enum bp_result bios_parser_get_encoder_cap_info( + struct dc_bios *dcb, + struct graphics_object_id object_id, +-- +2.7.4 + |