diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4363-drm-amd-Add-BIOS-smu_info-v3_3-required-struct-def.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4363-drm-amd-Add-BIOS-smu_info-v3_3-required-struct-def.patch | 225 |
1 files changed, 225 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4363-drm-amd-Add-BIOS-smu_info-v3_3-required-struct-def.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4363-drm-amd-Add-BIOS-smu_info-v3_3-required-struct-def.patch new file mode 100644 index 00000000..d2f16ca8 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4363-drm-amd-Add-BIOS-smu_info-v3_3-required-struct-def.patch @@ -0,0 +1,225 @@ +From b3cef6f7917e7e9d0452368db8c18b874835ce16 Mon Sep 17 00:00:00 2001 +From: "Jerry (Fangzhi) Zuo" <Jerry.Zuo@amd.com> +Date: Mon, 5 Mar 2018 14:59:57 -0500 +Subject: [PATCH 4363/5725] drm/amd: Add BIOS smu_info v3_3 required struct + def. + +Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> +Reviewed-by: Harry Wentland <harry.wentland@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/include/atomfirmware.h | 170 ++++++++++++++++++++++++++++- + 1 file changed, 168 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h +index 0f5ad54..de177ce 100644 +--- a/drivers/gpu/drm/amd/include/atomfirmware.h ++++ b/drivers/gpu/drm/amd/include/atomfirmware.h +@@ -501,6 +501,32 @@ enum atom_cooling_solution_id{ + LIQUID_COOLING = 0x01 + }; + ++struct atom_firmware_info_v3_2 { ++ struct atom_common_table_header table_header; ++ uint32_t firmware_revision; ++ uint32_t bootup_sclk_in10khz; ++ uint32_t bootup_mclk_in10khz; ++ uint32_t firmware_capability; // enum atombios_firmware_capability ++ uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ ++ uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address ++ uint16_t bootup_vddc_mv; ++ uint16_t bootup_vddci_mv; ++ uint16_t bootup_mvddc_mv; ++ uint16_t bootup_vddgfx_mv; ++ uint8_t mem_module_id; ++ uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ ++ uint8_t reserved1[2]; ++ uint32_t mc_baseaddr_high; ++ uint32_t mc_baseaddr_low; ++ uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def ++ uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id ++ uint8_t board_i2c_feature_slave_addr; ++ uint8_t reserved3; ++ uint16_t bootup_mvddq_mv; ++ uint16_t bootup_mvpp_mv; ++ uint32_t zfbstartaddrin16mb; ++ uint32_t reserved2[3]; ++}; + + /* + *************************************************************************** +@@ -1169,7 +1195,29 @@ struct atom_gfx_info_v2_2 + uint32_t rlc_gpu_timer_refclk; + }; + +- ++struct atom_gfx_info_v2_3 { ++ struct atom_common_table_header table_header; ++ uint8_t gfxip_min_ver; ++ uint8_t gfxip_max_ver; ++ uint8_t max_shader_engines; ++ uint8_t max_tile_pipes; ++ uint8_t max_cu_per_sh; ++ uint8_t max_sh_per_se; ++ uint8_t max_backends_per_se; ++ uint8_t max_texture_channel_caches; ++ uint32_t regaddr_cp_dma_src_addr; ++ uint32_t regaddr_cp_dma_src_addr_hi; ++ uint32_t regaddr_cp_dma_dst_addr; ++ uint32_t regaddr_cp_dma_dst_addr_hi; ++ uint32_t regaddr_cp_dma_command; ++ uint32_t regaddr_cp_status; ++ uint32_t regaddr_rlc_gpu_clock_32; ++ uint32_t rlc_gpu_timer_refclk; ++ uint8_t active_cu_per_sh; ++ uint8_t active_rb_per_se; ++ uint16_t gcgoldenoffset; ++ uint32_t rm21_sram_vmin_value; ++}; + + /* + *************************************************************************** +@@ -1198,6 +1246,76 @@ struct atom_smu_info_v3_1 + uint8_t fw_ctf_polarity; // GPIO polarity for CTF + }; + ++struct atom_smu_info_v3_2 { ++ struct atom_common_table_header table_header; ++ uint8_t smuip_min_ver; ++ uint8_t smuip_max_ver; ++ uint8_t smu_rsd1; ++ uint8_t gpuclk_ss_mode; ++ uint16_t sclk_ss_percentage; ++ uint16_t sclk_ss_rate_10hz; ++ uint16_t gpuclk_ss_percentage; // in unit of 0.001% ++ uint16_t gpuclk_ss_rate_10hz; ++ uint32_t core_refclk_10khz; ++ uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid ++ uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching ++ uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid ++ uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event ++ uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid ++ uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event ++ uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid ++ uint8_t fw_ctf_polarity; // GPIO polarity for CTF ++ uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid ++ uint8_t pcc_gpio_polarity; // GPIO polarity for CTF ++ uint16_t smugoldenoffset; ++ uint32_t gpupll_vco_freq_10khz; ++ uint32_t bootup_smnclk_10khz; ++ uint32_t bootup_socclk_10khz; ++ uint32_t bootup_mp0clk_10khz; ++ uint32_t bootup_mp1clk_10khz; ++ uint32_t bootup_lclk_10khz; ++ uint32_t bootup_dcefclk_10khz; ++ uint32_t ctf_threshold_override_value; ++ uint32_t reserved[5]; ++}; ++ ++struct atom_smu_info_v3_3 { ++ struct atom_common_table_header table_header; ++ uint8_t smuip_min_ver; ++ uint8_t smuip_max_ver; ++ uint8_t smu_rsd1; ++ uint8_t gpuclk_ss_mode; ++ uint16_t sclk_ss_percentage; ++ uint16_t sclk_ss_rate_10hz; ++ uint16_t gpuclk_ss_percentage; // in unit of 0.001% ++ uint16_t gpuclk_ss_rate_10hz; ++ uint32_t core_refclk_10khz; ++ uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid ++ uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching ++ uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid ++ uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event ++ uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid ++ uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event ++ uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid ++ uint8_t fw_ctf_polarity; // GPIO polarity for CTF ++ uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid ++ uint8_t pcc_gpio_polarity; // GPIO polarity for CTF ++ uint16_t smugoldenoffset; ++ uint32_t gpupll_vco_freq_10khz; ++ uint32_t bootup_smnclk_10khz; ++ uint32_t bootup_socclk_10khz; ++ uint32_t bootup_mp0clk_10khz; ++ uint32_t bootup_mp1clk_10khz; ++ uint32_t bootup_lclk_10khz; ++ uint32_t bootup_dcefclk_10khz; ++ uint32_t ctf_threshold_override_value; ++ uint32_t syspll3_0_vco_freq_10khz; ++ uint32_t syspll3_1_vco_freq_10khz; ++ uint32_t bootup_fclk_10khz; ++ uint32_t bootup_waflclk_10khz; ++ uint32_t reserved[3]; ++}; ++ + /* + *************************************************************************** + Data Table smc_dpm_info structure +@@ -1283,7 +1401,6 @@ struct atom_smc_dpm_info_v4_1 + uint32_t boardreserved[10]; + }; + +- + /* + *************************************************************************** + Data Table asic_profiling_info structure +@@ -1864,6 +1981,55 @@ enum atom_smu9_syspll0_clock_id + SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK + }; + ++enum atom_smu11_syspll_id { ++ SMU11_SYSPLL0_ID = 0, ++ SMU11_SYSPLL1_0_ID = 1, ++ SMU11_SYSPLL1_1_ID = 2, ++ SMU11_SYSPLL1_2_ID = 3, ++ SMU11_SYSPLL2_ID = 4, ++ SMU11_SYSPLL3_0_ID = 5, ++ SMU11_SYSPLL3_1_ID = 6, ++}; ++ ++ ++enum atom_smu11_syspll0_clock_id { ++ SMU11_SYSPLL0_SOCCLK_ID = 0, // SOCCLK ++ SMU11_SYSPLL0_MP0CLK_ID = 1, // MP0CLK ++ SMU11_SYSPLL0_DCLK_ID = 2, // DCLK ++ SMU11_SYSPLL0_VCLK_ID = 3, // VCLK ++ SMU11_SYSPLL0_ECLK_ID = 4, // ECLK ++ SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK ++}; ++ ++ ++enum atom_smu11_syspll1_0_clock_id { ++ SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a ++}; ++ ++enum atom_smu11_syspll1_1_clock_id { ++ SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b ++}; ++ ++enum atom_smu11_syspll1_2_clock_id { ++ SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK ++}; ++ ++enum atom_smu11_syspll2_clock_id { ++ SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK ++}; ++ ++enum atom_smu11_syspll3_0_clock_id { ++ SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK ++ SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK ++ SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK ++}; ++ ++enum atom_smu11_syspll3_1_clock_id { ++ SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK ++ SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK ++ SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK ++}; ++ + struct atom_get_smu_clock_info_output_parameters_v3_1 + { + union { +-- +2.7.4 + |