diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4218-drm-amd-display-add-calculated-clock-logging-to-DTN.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4218-drm-amd-display-add-calculated-clock-logging-to-DTN.patch | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4218-drm-amd-display-add-calculated-clock-logging-to-DTN.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4218-drm-amd-display-add-calculated-clock-logging-to-DTN.patch new file mode 100644 index 00000000..5cd610d4 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4218-drm-amd-display-add-calculated-clock-logging-to-DTN.patch @@ -0,0 +1,38 @@ +From 9fc34a808f4602ba9421d53654cd4e6918c94c4b Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Wed, 4 Apr 2018 16:03:38 -0400 +Subject: [PATCH 4218/5725] drm/amd/display: add calculated clock logging to + DTN + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 11 ++++++++++- + 1 file changed, 10 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index c9d4e96..468113d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -311,7 +311,16 @@ void dcn10_log_hw_state(struct dc *dc) + print_rq_dlg_ttu_regs(dc_ctx, &s); + DTN_INFO("\n"); + } +- DTN_INFO("\n"); ++ ++ DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n" ++ "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n", ++ dc->current_state->bw.dcn.calc_clk.dcfclk_khz, ++ dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz, ++ dc->current_state->bw.dcn.calc_clk.dispclk_khz, ++ dc->current_state->bw.dcn.calc_clk.dppclk_khz, ++ dc->current_state->bw.dcn.calc_clk.max_supported_dppclk_khz, ++ dc->current_state->bw.dcn.calc_clk.fclk_khz, ++ dc->current_state->bw.dcn.calc_clk.socclk_khz); + + log_mpc_crc(dc); + +-- +2.7.4 + |