diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/4186-drm-amdgpu-gfx9-add-emit_reg_write_reg_wait-ring-cal.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/4186-drm-amdgpu-gfx9-add-emit_reg_write_reg_wait-ring-cal.patch | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/4186-drm-amdgpu-gfx9-add-emit_reg_write_reg_wait-ring-cal.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/4186-drm-amdgpu-gfx9-add-emit_reg_write_reg_wait-ring-cal.patch new file mode 100644 index 00000000..2fc05496 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/4186-drm-amdgpu-gfx9-add-emit_reg_write_reg_wait-ring-cal.patch @@ -0,0 +1,70 @@ +From 32e132e631bce83c114a4000765db9c6a5ebd027 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Tue, 27 Mar 2018 15:07:50 -0500 +Subject: [PATCH 4186/5725] drm/amdgpu/gfx9: add emit_reg_write_reg_wait ring + callback (v2) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +This adds support for writing and reading back in a single +oneshot packet. This is needed to send a tlb invalidation +and wait for ack in a single operation. + +v2: squash the gfx ring stall fix + +Reviewed-by: Huang Rui <ray.huang@amd.com> +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Emily Deng <Emily.Deng@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index ba036af..c407f1f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -4220,6 +4220,15 @@ static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, + gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); + } + ++static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, ++ uint32_t reg0, uint32_t reg1, ++ uint32_t ref, uint32_t mask) ++{ ++ int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); ++ ++ gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, ref, mask, 0x20); ++} ++ + static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, + enum amdgpu_interrupt_state state) + { +@@ -4542,6 +4551,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { + .emit_tmz = gfx_v9_0_ring_emit_tmz, + .emit_wreg = gfx_v9_0_ring_emit_wreg, + .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, ++ .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, + }; + + static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { +@@ -4577,6 +4587,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { + .set_priority = gfx_v9_0_ring_set_priority_compute, + .emit_wreg = gfx_v9_0_ring_emit_wreg, + .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, ++ .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, + }; + + static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { +@@ -4607,6 +4618,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { + .emit_rreg = gfx_v9_0_ring_emit_rreg, + .emit_wreg = gfx_v9_0_ring_emit_wreg, + .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, ++ .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, + }; + + static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev) +-- +2.7.4 + |