diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/1452-drm-amdkfd-Move-PM4-Release_Mem-headers.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/1452-drm-amdkfd-Move-PM4-Release_Mem-headers.patch | 235 |
1 files changed, 235 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/1452-drm-amdkfd-Move-PM4-Release_Mem-headers.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/1452-drm-amdkfd-Move-PM4-Release_Mem-headers.patch new file mode 100644 index 00000000..5d33ea06 --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/1452-drm-amdkfd-Move-PM4-Release_Mem-headers.patch @@ -0,0 +1,235 @@ +From e656f267ae5d9b1b44f42cbff593a574d7bf01ce Mon Sep 17 00:00:00 2001 +From: Amber Lin <Amber.Lin@amd.com> +Date: Wed, 15 Jun 2016 16:59:47 -0400 +Subject: [PATCH 1452/4131] drm/amdkfd: Move PM4 Release_Mem headers + +Move PM4 Release_Mem headers from kfd_pm4_headers_diq.h to +kfd_pm4_headers.h so it can be used not only on DIQ but also on other +queues. + +BUG: SWDEV-93847 + +Change-Id: I7cf20819e75a8bea78bdd5b82f92551a9d1bb3ae +Signed-off-by: Amber Lin <Amber.Lin@amd.com> +--- + drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h | 95 +++++++++++++++++++++++ + drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h | 97 ------------------------ + 2 files changed, 95 insertions(+), 97 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h +index e7570cc..058ba1b 100644 +--- a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h ++++ b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers.h +@@ -518,6 +518,101 @@ struct pm4_unmap_queues { + }; + #endif + ++/*--------------------_RELEASE_MEM-------------------- */ ++ ++#ifndef PM4__RELEASE_MEM_DEFINED ++#define PM4__RELEASE_MEM_DEFINED ++enum RELEASE_MEM_event_index_enum { ++ event_index___release_mem__end_of_pipe = 5, ++ event_index___release_mem__shader_done = 6 ++}; ++ ++enum RELEASE_MEM_cache_policy_enum { ++ cache_policy___release_mem__lru = 0, ++ cache_policy___release_mem__stream = 1, ++ cache_policy___release_mem__bypass = 2 ++}; ++ ++enum RELEASE_MEM_dst_sel_enum { ++ dst_sel___release_mem__memory_controller = 0, ++ dst_sel___release_mem__tc_l2 = 1, ++ dst_sel___release_mem__queue_write_pointer_register = 2, ++ dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3 ++}; ++ ++enum RELEASE_MEM_int_sel_enum { ++ int_sel___release_mem__none = 0, ++ int_sel___release_mem__send_interrupt_only = 1, ++ int_sel___release_mem__send_interrupt_after_write_confirm = 2, ++ int_sel___release_mem__send_data_after_write_confirm = 3 ++}; ++ ++enum RELEASE_MEM_data_sel_enum { ++ data_sel___release_mem__none = 0, ++ data_sel___release_mem__send_32_bit_low = 1, ++ data_sel___release_mem__send_64_bit_data = 2, ++ data_sel___release_mem__send_gpu_clock_counter = 3, ++ data_sel___release_mem__send_cp_perfcounter_hi_lo = 4, ++ data_sel___release_mem__store_gds_data_to_memory = 5 ++}; ++ ++struct pm4__release_mem { ++ union { ++ union PM4_MES_TYPE_3_HEADER header; /*header */ ++ unsigned int ordinal1; ++ }; ++ ++ union { ++ struct { ++ unsigned int event_type:6; ++ unsigned int reserved1:2; ++ enum RELEASE_MEM_event_index_enum event_index:4; ++ unsigned int tcl1_vol_action_ena:1; ++ unsigned int tc_vol_action_ena:1; ++ unsigned int reserved2:1; ++ unsigned int tc_wb_action_ena:1; ++ unsigned int tcl1_action_ena:1; ++ unsigned int tc_action_ena:1; ++ unsigned int reserved3:6; ++ unsigned int atc:1; ++ enum RELEASE_MEM_cache_policy_enum cache_policy:2; ++ unsigned int reserved4:5; ++ } bitfields2; ++ unsigned int ordinal2; ++ }; ++ ++ union { ++ struct { ++ unsigned int reserved5:16; ++ enum RELEASE_MEM_dst_sel_enum dst_sel:2; ++ unsigned int reserved6:6; ++ enum RELEASE_MEM_int_sel_enum int_sel:3; ++ unsigned int reserved7:2; ++ enum RELEASE_MEM_data_sel_enum data_sel:3; ++ } bitfields3; ++ unsigned int ordinal3; ++ }; ++ ++ union { ++ struct { ++ unsigned int reserved8:2; ++ unsigned int address_lo_32b:30; ++ } bitfields4; ++ struct { ++ unsigned int reserved9:3; ++ unsigned int address_lo_64b:29; ++ } bitfields5; ++ unsigned int ordinal4; ++ }; ++ ++ unsigned int address_hi; ++ ++ unsigned int data_lo; ++ ++ unsigned int data_hi; ++}; ++#endif ++ + enum { + CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014 + }; +diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h +index a0ff348..0b314a8 100644 +--- a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h ++++ b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_diq.h +@@ -77,103 +77,6 @@ struct pm4__indirect_buffer_pasid { + + #endif + +-/*--------------------_RELEASE_MEM-------------------- */ +- +-#ifndef _PM4__RELEASE_MEM_DEFINED +-#define _PM4__RELEASE_MEM_DEFINED +-enum _RELEASE_MEM_event_index_enum { +- event_index___release_mem__end_of_pipe = 5, +- event_index___release_mem__shader_done = 6 +-}; +- +-enum _RELEASE_MEM_cache_policy_enum { +- cache_policy___release_mem__lru = 0, +- cache_policy___release_mem__stream = 1, +- cache_policy___release_mem__bypass = 2 +-}; +- +-enum _RELEASE_MEM_dst_sel_enum { +- dst_sel___release_mem__memory_controller = 0, +- dst_sel___release_mem__tc_l2 = 1, +- dst_sel___release_mem__queue_write_pointer_register = 2, +- dst_sel___release_mem__queue_write_pointer_poll_mask_bit = 3 +-}; +- +-enum _RELEASE_MEM_int_sel_enum { +- int_sel___release_mem__none = 0, +- int_sel___release_mem__send_interrupt_only = 1, +- int_sel___release_mem__send_interrupt_after_write_confirm = 2, +- int_sel___release_mem__send_data_after_write_confirm = 3 +-}; +- +-enum _RELEASE_MEM_data_sel_enum { +- data_sel___release_mem__none = 0, +- data_sel___release_mem__send_32_bit_low = 1, +- data_sel___release_mem__send_64_bit_data = 2, +- data_sel___release_mem__send_gpu_clock_counter = 3, +- data_sel___release_mem__send_cp_perfcounter_hi_lo = 4, +- data_sel___release_mem__store_gds_data_to_memory = 5 +-}; +- +-struct pm4__release_mem { +- union { +- union PM4_MES_TYPE_3_HEADER header; /*header */ +- unsigned int ordinal1; +- }; +- +- union { +- struct { +- unsigned int event_type:6; +- unsigned int reserved1:2; +- enum _RELEASE_MEM_event_index_enum event_index:4; +- unsigned int tcl1_vol_action_ena:1; +- unsigned int tc_vol_action_ena:1; +- unsigned int reserved2:1; +- unsigned int tc_wb_action_ena:1; +- unsigned int tcl1_action_ena:1; +- unsigned int tc_action_ena:1; +- unsigned int reserved3:6; +- unsigned int atc:1; +- enum _RELEASE_MEM_cache_policy_enum cache_policy:2; +- unsigned int reserved4:5; +- } bitfields2; +- unsigned int ordinal2; +- }; +- +- union { +- struct { +- unsigned int reserved5:16; +- enum _RELEASE_MEM_dst_sel_enum dst_sel:2; +- unsigned int reserved6:6; +- enum _RELEASE_MEM_int_sel_enum int_sel:3; +- unsigned int reserved7:2; +- enum _RELEASE_MEM_data_sel_enum data_sel:3; +- } bitfields3; +- unsigned int ordinal3; +- }; +- +- union { +- struct { +- unsigned int reserved8:2; +- unsigned int address_lo_32b:30; +- } bitfields4; +- struct { +- unsigned int reserved9:3; +- unsigned int address_lo_64b:29; +- } bitfields5; +- unsigned int ordinal4; +- }; +- +- unsigned int address_hi; +- +- unsigned int data_lo; +- +- unsigned int data_hi; +- +-}; +-#endif +- +- + /*--------------------_SET_CONFIG_REG-------------------- */ + + #ifndef _PM4__SET_CONFIG_REG_DEFINED +-- +2.7.4 + |