aboutsummaryrefslogtreecommitdiffstats
path: root/common/recipes-kernel/linux/linux-yocto-4.14.71/1051-drm-amdgpu-unify-the-interface-of-amd_pm_funcs.patch
diff options
context:
space:
mode:
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/1051-drm-amdgpu-unify-the-interface-of-amd_pm_funcs.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/1051-drm-amdgpu-unify-the-interface-of-amd_pm_funcs.patch1006
1 files changed, 1006 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/1051-drm-amdgpu-unify-the-interface-of-amd_pm_funcs.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/1051-drm-amdgpu-unify-the-interface-of-amd_pm_funcs.patch
new file mode 100644
index 00000000..a2d0448e
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/1051-drm-amdgpu-unify-the-interface-of-amd_pm_funcs.patch
@@ -0,0 +1,1006 @@
+From 6db20015de6f1cc23274aec33367d9968463c423 Mon Sep 17 00:00:00 2001
+From: Rex Zhu <Rex.Zhu@amd.com>
+Date: Wed, 6 Sep 2017 18:43:52 +0800
+Subject: [PATCH 1051/4131] drm/amdgpu: unify the interface of amd_pm_funcs
+
+put amd_pm_funcs table in struct powerplay for all
+asics.
+
+Change-Id: I2fe7cbcd37afbe2b7dfb42800f84e4c0ae97b49a
+Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 120 ++++++-------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 240 +++++++++++---------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 3 +
+ drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 10 +-
+ drivers/gpu/drm/amd/amdgpu/cik_dpm.h | 3 +-
+ drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 10 +-
+ drivers/gpu/drm/amd/amdgpu/si_dpm.c | 10 +-
+ drivers/gpu/drm/amd/amdgpu/si_dpm.h | 1 +
+ 9 files changed, 163 insertions(+), 239 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+index 2b083d7..f032e87 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -3570,10 +3570,7 @@ static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
+
+ valuesize = sizeof(values);
+ if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
+- r = adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, idx, &values[0], &valuesize);
+- else if (adev->pm.funcs && adev->pm.funcs->read_sensor)
+- r = adev->pm.funcs->read_sensor(adev, idx, &values[0],
+- &valuesize);
++ r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
+ else
+ return -EINVAL;
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+index 5b2b724..0d22259 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+@@ -241,134 +241,119 @@ enum amdgpu_pcie_gen {
+ AMDGPU_PCIE_GEN_INVALID = 0xffff
+ };
+
+-#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
+-#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
+-#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
+-#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
+-#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
+-#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
+-#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
++#define amdgpu_dpm_pre_set_power_state(adev) \
++ ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
++
++#define amdgpu_dpm_set_power_state(adev) \
++ ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
++
++#define amdgpu_dpm_post_set_power_state(adev) \
++ ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle))
++
++#define amdgpu_dpm_display_configuration_changed(adev) \
++ ((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle))
++
++#define amdgpu_dpm_print_power_state(adev, ps) \
++ ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps)))
++
++#define amdgpu_dpm_vblank_too_short(adev) \
++ ((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle))
++
++#define amdgpu_dpm_enable_bapm(adev, e) \
++ ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
+
+ #define amdgpu_dpm_read_sensor(adev, idx, value, size) \
+- ((adev)->pp_enabled ? \
+- (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value), (size)) : \
+- (adev)->pm.funcs->read_sensor((adev), (idx), (value), (size)))
++ ((adev)->powerplay.pp_funcs->read_sensor((adev)->powerplay.pp_handle, (idx), (value), (size)))
+
+ #define amdgpu_dpm_get_temperature(adev) \
+- ((adev)->pp_enabled ? \
+- (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
+- (adev)->pm.funcs->get_temperature((adev)))
++ ((adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle))
+
+ #define amdgpu_dpm_set_fan_control_mode(adev, m) \
+- ((adev)->pp_enabled ? \
+- (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
+- (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
++ ((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)))
+
+ #define amdgpu_dpm_get_fan_control_mode(adev) \
+- ((adev)->pp_enabled ? \
+- (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
+- (adev)->pm.funcs->get_fan_control_mode((adev)))
++ ((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle))
+
+ #define amdgpu_dpm_set_fan_speed_percent(adev, s) \
+- ((adev)->pp_enabled ? \
+- (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
+- (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
++ ((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
+
+ #define amdgpu_dpm_get_fan_speed_percent(adev, s) \
+- ((adev)->pp_enabled ? \
+- (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
+- (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
++ ((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)))
+
+ #define amdgpu_dpm_get_fan_speed_rpm(adev, s) \
+- ((adev)->pp_enabled ? \
+- (adev)->powerplay.pp_funcs->get_fan_speed_rpm((adev)->powerplay.pp_handle, (s)) : \
+- -EINVAL)
++ ((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s))
+
+ #define amdgpu_dpm_get_sclk(adev, l) \
+- ((adev)->pp_enabled ? \
+- (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
+- (adev)->pm.funcs->get_sclk((adev), (l)))
++ ((adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)))
+
+ #define amdgpu_dpm_get_mclk(adev, l) \
+- ((adev)->pp_enabled ? \
+- (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
+- (adev)->pm.funcs->get_mclk((adev), (l)))
+-
++ ((adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)))
+
+ #define amdgpu_dpm_force_performance_level(adev, l) \
+- ((adev)->pp_enabled ? \
+- (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
+- (adev)->pm.funcs->force_performance_level((adev), (l)))
++ ((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)))
+
+ #define amdgpu_dpm_powergate_uvd(adev, g) \
+- ((adev)->pp_enabled ? \
+- (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
+- (adev)->pm.funcs->powergate_uvd((adev), (g)))
++ ((adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)))
+
+ #define amdgpu_dpm_powergate_vce(adev, g) \
+- ((adev)->pp_enabled ? \
+- (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
+- (adev)->pm.funcs->powergate_vce((adev), (g)))
++ ((adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)))
+
+ #define amdgpu_dpm_get_current_power_state(adev) \
+- (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
++ ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle))
+
+ #define amdgpu_dpm_get_pp_num_states(adev, data) \
+- (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
++ ((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data))
+
+ #define amdgpu_dpm_get_pp_table(adev, table) \
+- (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
++ ((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table))
+
+ #define amdgpu_dpm_set_pp_table(adev, buf, size) \
+- (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
++ ((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size))
+
+ #define amdgpu_dpm_print_clock_levels(adev, type, buf) \
+- (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
++ ((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf))
+
+ #define amdgpu_dpm_force_clock_level(adev, type, level) \
+- (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
++ ((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level))
+
+ #define amdgpu_dpm_get_sclk_od(adev) \
+- (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
++ ((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle))
+
+ #define amdgpu_dpm_set_sclk_od(adev, value) \
+- (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
++ ((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value))
+
+ #define amdgpu_dpm_get_mclk_od(adev) \
+- ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
++ ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
+
+ #define amdgpu_dpm_set_mclk_od(adev, value) \
+- ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
++ ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
+
+ #define amdgpu_dpm_dispatch_task(adev, task_id, input, output) \
+- ((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (input), (output))
++ ((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (input), (output))
+
+-#define amgdpu_dpm_check_state_equal(adev, cps, rps, equal) (adev)->pm.funcs->check_state_equal((adev), (cps),(rps),(equal))
++#define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \
++ ((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal)))
+
+ #define amdgpu_dpm_get_vce_clock_state(adev, i) \
+- ((adev)->pp_enabled ? \
+- (adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)) : \
+- (adev)->pm.funcs->get_vce_clock_state((adev), (i)))
++ ((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)))
+
+-#define amdgpu_dpm_get_performance_level(adev) \
+- ((adev)->pp_enabled ? \
+- (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle) : \
+- (adev)->pm.dpm.forced_level)
++#define amdgpu_dpm_get_performance_level(adev) \
++ ((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle))
+
+ #define amdgpu_dpm_reset_power_profile_state(adev, request) \
+- ((adev)->powerplay.pp_funcs->reset_power_profile_state(\
++ ((adev)->powerplay.pp_funcs->reset_power_profile_state(\
+ (adev)->powerplay.pp_handle, request))
+
+ #define amdgpu_dpm_get_power_profile_state(adev, query) \
+- ((adev)->powerplay.pp_funcs->get_power_profile_state(\
++ ((adev)->powerplay.pp_funcs->get_power_profile_state(\
+ (adev)->powerplay.pp_handle, query))
+
+ #define amdgpu_dpm_set_power_profile_state(adev, request) \
+- ((adev)->powerplay.pp_funcs->set_power_profile_state(\
++ ((adev)->powerplay.pp_funcs->set_power_profile_state(\
+ (adev)->powerplay.pp_handle, request))
+
+ #define amdgpu_dpm_switch_power_profile(adev, type) \
+- ((adev)->powerplay.pp_funcs->switch_power_profile(\
++ ((adev)->powerplay.pp_funcs->switch_power_profile(\
+ (adev)->powerplay.pp_handle, type))
+
+ struct amdgpu_dpm {
+@@ -442,7 +427,6 @@ struct amdgpu_pm {
+ struct amdgpu_dpm dpm;
+ const struct firmware *fw; /* SMC firmware */
+ uint32_t fw_version;
+- const struct amd_pm_funcs *funcs;
+ uint32_t pcie_gen_mask;
+ uint32_t pcie_mlw_mask;
+ struct amd_pp_display_configuration pm_display_cfg;/* set by dc */
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+index e78395a..74539c2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+@@ -74,7 +74,7 @@ void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
+ adev->pm.dpm.ac_power = true;
+ else
+ adev->pm.dpm.ac_power = false;
+- if (adev->pm.funcs->enable_bapm)
++ if (adev->powerplay.pp_funcs->enable_bapm)
+ amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
+ mutex_unlock(&adev->pm.mutex);
+ }
+@@ -88,9 +88,9 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
+ struct amdgpu_device *adev = ddev->dev_private;
+ enum amd_pm_state_type pm;
+
+- if (adev->pp_enabled) {
++ if (adev->powerplay.pp_funcs->get_current_power_state)
+ pm = amdgpu_dpm_get_current_power_state(adev);
+- } else
++ else
+ pm = adev->pm.dpm.user_state;
+
+ return snprintf(buf, PAGE_SIZE, "%s\n",
+@@ -140,13 +140,17 @@ static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
+ {
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+- enum amd_dpm_forced_level level;
++ enum amd_dpm_forced_level level = 0xff;
+
+ if ((adev->flags & AMD_IS_PX) &&
+ (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+ return snprintf(buf, PAGE_SIZE, "off\n");
+
+- level = amdgpu_dpm_get_performance_level(adev);
++ if (adev->powerplay.pp_funcs->get_performance_level)
++ level = amdgpu_dpm_get_performance_level(adev);
++ else
++ level = adev->pm.dpm.forced_level;
++
+ return snprintf(buf, PAGE_SIZE, "%s\n",
+ (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
+ (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
+@@ -167,7 +171,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+ enum amd_dpm_forced_level level;
+- enum amd_dpm_forced_level current_level;
++ enum amd_dpm_forced_level current_level = 0xff;
+ int ret = 0;
+
+ /* Can't force performance level when the card is off */
+@@ -175,7 +179,8 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
+ (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+ return -EINVAL;
+
+- current_level = amdgpu_dpm_get_performance_level(adev);
++ if (adev->powerplay.pp_funcs->get_performance_level)
++ current_level = amdgpu_dpm_get_performance_level(adev);
+
+ if (strncmp("low", buf, strlen("low")) == 0) {
+ level = AMD_DPM_FORCED_LEVEL_LOW;
+@@ -203,9 +208,7 @@ static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
+ if (current_level == level)
+ return count;
+
+- if (adev->pp_enabled)
+- amdgpu_dpm_force_performance_level(adev, level);
+- else {
++ if (adev->powerplay.pp_funcs->force_performance_level) {
+ mutex_lock(&adev->pm.mutex);
+ if (adev->pm.dpm.thermal_active) {
+ count = -EINVAL;
+@@ -233,7 +236,7 @@ static ssize_t amdgpu_get_pp_num_states(struct device *dev,
+ struct pp_states_info data;
+ int i, buf_len;
+
+- if (adev->pp_enabled)
++ if (adev->powerplay.pp_funcs->get_pp_num_states)
+ amdgpu_dpm_get_pp_num_states(adev, &data);
+
+ buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
+@@ -257,8 +260,8 @@ static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
+ enum amd_pm_state_type pm = 0;
+ int i = 0;
+
+- if (adev->pp_enabled) {
+-
++ if (adev->powerplay.pp_funcs->get_current_power_state
++ && adev->powerplay.pp_funcs->get_pp_num_states) {
+ pm = amdgpu_dpm_get_current_power_state(adev);
+ amdgpu_dpm_get_pp_num_states(adev, &data);
+
+@@ -280,25 +283,10 @@ static ssize_t amdgpu_get_pp_force_state(struct device *dev,
+ {
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+- struct pp_states_info data;
+- enum amd_pm_state_type pm = 0;
+- int i;
+-
+- if (adev->pp_force_state_enabled && adev->pp_enabled) {
+- pm = amdgpu_dpm_get_current_power_state(adev);
+- amdgpu_dpm_get_pp_num_states(adev, &data);
+-
+- for (i = 0; i < data.nums; i++) {
+- if (pm == data.states[i])
+- break;
+- }
+
+- if (i == data.nums)
+- i = -EINVAL;
+-
+- return snprintf(buf, PAGE_SIZE, "%d\n", i);
+-
+- } else
++ if (adev->pp_force_state_enabled)
++ return amdgpu_get_pp_cur_state(dev, attr, buf);
++ else
+ return snprintf(buf, PAGE_SIZE, "\n");
+ }
+
+@@ -347,7 +335,7 @@ static ssize_t amdgpu_get_pp_table(struct device *dev,
+ char *table = NULL;
+ int size;
+
+- if (adev->pp_enabled)
++ if (adev->powerplay.pp_funcs->get_pp_table)
+ size = amdgpu_dpm_get_pp_table(adev, &table);
+ else
+ return 0;
+@@ -368,7 +356,7 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+
+- if (adev->pp_enabled)
++ if (adev->powerplay.pp_funcs->set_pp_table)
+ amdgpu_dpm_set_pp_table(adev, buf, count);
+
+ return count;
+@@ -380,14 +368,11 @@ static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
+ {
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+- ssize_t size = 0;
+-
+- if (adev->pp_enabled)
+- size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
+- else if (adev->pm.funcs->print_clock_levels)
+- size = adev->pm.funcs->print_clock_levels(adev, PP_SCLK, buf);
+
+- return size;
++ if (adev->powerplay.pp_funcs->print_clock_levels)
++ return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
++ else
++ return snprintf(buf, PAGE_SIZE, "\n");
+ }
+
+ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
+@@ -416,10 +401,9 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
+ mask |= 1 << level;
+ }
+
+- if (adev->pp_enabled)
++ if (adev->powerplay.pp_funcs->force_clock_level)
+ amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
+- else if (adev->pm.funcs->force_clock_level)
+- adev->pm.funcs->force_clock_level(adev, PP_SCLK, mask);
++
+ fail:
+ return count;
+ }
+@@ -430,14 +414,11 @@ static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
+ {
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+- ssize_t size = 0;
+-
+- if (adev->pp_enabled)
+- size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
+- else if (adev->pm.funcs->print_clock_levels)
+- size = adev->pm.funcs->print_clock_levels(adev, PP_MCLK, buf);
+
+- return size;
++ if (adev->powerplay.pp_funcs->print_clock_levels)
++ return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
++ else
++ return snprintf(buf, PAGE_SIZE, "\n");
+ }
+
+ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
+@@ -465,11 +446,9 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
+ }
+ mask |= 1 << level;
+ }
+-
+- if (adev->pp_enabled)
++ if (adev->powerplay.pp_funcs->force_clock_level)
+ amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
+- else if (adev->pm.funcs->force_clock_level)
+- adev->pm.funcs->force_clock_level(adev, PP_MCLK, mask);
++
+ fail:
+ return count;
+ }
+@@ -480,14 +459,11 @@ static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
+ {
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+- ssize_t size = 0;
+-
+- if (adev->pp_enabled)
+- size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
+- else if (adev->pm.funcs->print_clock_levels)
+- size = adev->pm.funcs->print_clock_levels(adev, PP_PCIE, buf);
+
+- return size;
++ if (adev->powerplay.pp_funcs->print_clock_levels)
++ return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
++ else
++ return snprintf(buf, PAGE_SIZE, "\n");
+ }
+
+ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
+@@ -515,11 +491,9 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
+ }
+ mask |= 1 << level;
+ }
+-
+- if (adev->pp_enabled)
++ if (adev->powerplay.pp_funcs->force_clock_level)
+ amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
+- else if (adev->pm.funcs->force_clock_level)
+- adev->pm.funcs->force_clock_level(adev, PP_PCIE, mask);
++
+ fail:
+ return count;
+ }
+@@ -532,10 +506,8 @@ static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
+ struct amdgpu_device *adev = ddev->dev_private;
+ uint32_t value = 0;
+
+- if (adev->pp_enabled)
++ if (adev->powerplay.pp_funcs->get_sclk_od)
+ value = amdgpu_dpm_get_sclk_od(adev);
+- else if (adev->pm.funcs->get_sclk_od)
+- value = adev->pm.funcs->get_sclk_od(adev);
+
+ return snprintf(buf, PAGE_SIZE, "%d\n", value);
+ }
+@@ -556,12 +528,12 @@ static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
+ count = -EINVAL;
+ goto fail;
+ }
++ if (adev->powerplay.pp_funcs->set_sclk_od)
++ amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
+
+ if (adev->pp_enabled) {
+- amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
+ amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
+- } else if (adev->pm.funcs->set_sclk_od) {
+- adev->pm.funcs->set_sclk_od(adev, (uint32_t)value);
++ } else {
+ adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
+ amdgpu_pm_compute_clocks(adev);
+ }
+@@ -578,10 +550,8 @@ static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
+ struct amdgpu_device *adev = ddev->dev_private;
+ uint32_t value = 0;
+
+- if (adev->pp_enabled)
++ if (adev->powerplay.pp_funcs->get_mclk_od)
+ value = amdgpu_dpm_get_mclk_od(adev);
+- else if (adev->pm.funcs->get_mclk_od)
+- value = adev->pm.funcs->get_mclk_od(adev);
+
+ return snprintf(buf, PAGE_SIZE, "%d\n", value);
+ }
+@@ -602,12 +572,12 @@ static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
+ count = -EINVAL;
+ goto fail;
+ }
++ if (adev->powerplay.pp_funcs->set_mclk_od)
++ amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
+
+ if (adev->pp_enabled) {
+- amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
+ amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL, NULL);
+- } else if (adev->pm.funcs->set_mclk_od) {
+- adev->pm.funcs->set_mclk_od(adev, (uint32_t)value);
++ } else {
+ adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
+ amdgpu_pm_compute_clocks(adev);
+ }
+@@ -621,14 +591,11 @@ static ssize_t amdgpu_get_pp_power_profile(struct device *dev,
+ {
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = ddev->dev_private;
+- int ret = 0;
++ int ret = 0xff;
+
+- if (adev->pp_enabled)
++ if (adev->powerplay.pp_funcs->get_power_profile_state)
+ ret = amdgpu_dpm_get_power_profile_state(
+ adev, query);
+- else if (adev->pm.funcs->get_power_profile_state)
+- ret = adev->pm.funcs->get_power_profile_state(
+- adev, query);
+
+ if (ret)
+ return ret;
+@@ -675,15 +642,12 @@ static ssize_t amdgpu_set_pp_power_profile(struct device *dev,
+ char *sub_str, buf_cpy[128], *tmp_str;
+ const char delimiter[3] = {' ', '\n', '\0'};
+ long int value;
+- int ret = 0;
++ int ret = 0xff;
+
+ if (strncmp("reset", buf, strlen("reset")) == 0) {
+- if (adev->pp_enabled)
++ if (adev->powerplay.pp_funcs->reset_power_profile_state)
+ ret = amdgpu_dpm_reset_power_profile_state(
+ adev, request);
+- else if (adev->pm.funcs->reset_power_profile_state)
+- ret = adev->pm.funcs->reset_power_profile_state(
+- adev, request);
+ if (ret) {
+ count = -EINVAL;
+ goto fail;
+@@ -692,12 +656,10 @@ static ssize_t amdgpu_set_pp_power_profile(struct device *dev,
+ }
+
+ if (strncmp("set", buf, strlen("set")) == 0) {
+- if (adev->pp_enabled)
++ if (adev->powerplay.pp_funcs->set_power_profile_state)
+ ret = amdgpu_dpm_set_power_profile_state(
+ adev, request);
+- else if (adev->pm.funcs->set_power_profile_state)
+- ret = adev->pm.funcs->set_power_profile_state(
+- adev, request);
++
+ if (ret) {
+ count = -EINVAL;
+ goto fail;
+@@ -745,13 +707,8 @@ static ssize_t amdgpu_set_pp_power_profile(struct device *dev,
+
+ loop++;
+ }
+-
+- if (adev->pp_enabled)
+- ret = amdgpu_dpm_set_power_profile_state(
+- adev, request);
+- else if (adev->pm.funcs->set_power_profile_state)
+- ret = adev->pm.funcs->set_power_profile_state(
+- adev, request);
++ if (adev->powerplay.pp_funcs->set_power_profile_state)
++ ret = amdgpu_dpm_set_power_profile_state(adev, request);
+
+ if (ret)
+ count = -EINVAL;
+@@ -831,7 +788,7 @@ static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
+ (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+ return -EINVAL;
+
+- if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
++ if (!adev->powerplay.pp_funcs->get_temperature)
+ temp = 0;
+ else
+ temp = amdgpu_dpm_get_temperature(adev);
+@@ -862,7 +819,7 @@ static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
+ struct amdgpu_device *adev = dev_get_drvdata(dev);
+ u32 pwm_mode = 0;
+
+- if (!adev->pp_enabled && !adev->pm.funcs->get_fan_control_mode)
++ if (!adev->powerplay.pp_funcs->get_fan_control_mode)
+ return -EINVAL;
+
+ pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
+@@ -879,7 +836,7 @@ static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
+ int err;
+ int value;
+
+- if (!adev->pp_enabled && !adev->pm.funcs->set_fan_control_mode)
++ if (!adev->powerplay.pp_funcs->set_fan_control_mode)
+ return -EINVAL;
+
+ err = kstrtoint(buf, 10, &value);
+@@ -919,9 +876,11 @@ static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
+
+ value = (value * 100) / 255;
+
+- err = amdgpu_dpm_set_fan_speed_percent(adev, value);
+- if (err)
+- return err;
++ if (adev->powerplay.pp_funcs->set_fan_speed_percent) {
++ err = amdgpu_dpm_set_fan_speed_percent(adev, value);
++ if (err)
++ return err;
++ }
+
+ return count;
+ }
+@@ -932,11 +891,13 @@ static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
+ {
+ struct amdgpu_device *adev = dev_get_drvdata(dev);
+ int err;
+- u32 speed;
++ u32 speed = 0;
+
+- err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
+- if (err)
+- return err;
++ if (adev->powerplay.pp_funcs->get_fan_speed_percent) {
++ err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
++ if (err)
++ return err;
++ }
+
+ speed = (speed * 255) / 100;
+
+@@ -949,11 +910,13 @@ static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
+ {
+ struct amdgpu_device *adev = dev_get_drvdata(dev);
+ int err;
+- u32 speed;
++ u32 speed = 0;
+
+- err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
+- if (err)
+- return err;
++ if (adev->powerplay.pp_funcs->get_fan_speed_rpm) {
++ err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
++ if (err)
++ return err;
++ }
+
+ return sprintf(buf, "%i\n", speed);
+ }
+@@ -1008,21 +971,21 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
+ return 0;
+
+ /* mask fan attributes if we have no bindings for this asic to expose */
+- if ((!adev->pm.funcs->get_fan_speed_percent &&
++ if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
+ attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
+- (!adev->pm.funcs->get_fan_control_mode &&
++ (!adev->powerplay.pp_funcs->get_fan_control_mode &&
+ attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
+ effective_mode &= ~S_IRUGO;
+
+- if ((!adev->pm.funcs->set_fan_speed_percent &&
++ if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
+ attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
+- (!adev->pm.funcs->set_fan_control_mode &&
++ (!adev->powerplay.pp_funcs->set_fan_control_mode &&
+ attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
+ effective_mode &= ~S_IWUSR;
+
+ /* hide max/min values if we can't both query and manage the fan */
+- if ((!adev->pm.funcs->set_fan_speed_percent &&
+- !adev->pm.funcs->get_fan_speed_percent) &&
++ if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
++ !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
+ (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
+ attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
+ return 0;
+@@ -1055,7 +1018,7 @@ void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
+ if (!adev->pm.dpm_enabled)
+ return;
+
+- if (adev->pm.funcs->get_temperature) {
++ if (adev->powerplay.pp_funcs->get_temperature) {
+ int temp = amdgpu_dpm_get_temperature(adev);
+
+ if (temp < adev->pm.dpm.thermal.min_temp)
+@@ -1087,7 +1050,7 @@ static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
+ true : false;
+
+ /* check if the vblank period is too short to adjust the mclk */
+- if (single_display && adev->pm.funcs->vblank_too_short) {
++ if (single_display && adev->powerplay.pp_funcs->vblank_too_short) {
+ if (amdgpu_dpm_vblank_too_short(adev))
+ single_display = false;
+ }
+@@ -1216,7 +1179,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
+ struct amdgpu_ps *ps;
+ enum amd_pm_state_type dpm_state;
+ int ret;
+- bool equal;
++ bool equal = false;
+
+ /* if dpm init failed */
+ if (!adev->pm.dpm_enabled)
+@@ -1236,7 +1199,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
+ else
+ return;
+
+- if (amdgpu_dpm == 1) {
++ if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) {
+ printk("switching from power state:\n");
+ amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
+ printk("switching to power state:\n");
+@@ -1244,15 +1207,17 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
+ }
+ /* update whether vce is active */
+ ps->vce_active = adev->pm.dpm.vce_active;
+-
+- amdgpu_dpm_display_configuration_changed(adev);
++ if (adev->powerplay.pp_funcs->display_configuration_changed)
++ amdgpu_dpm_display_configuration_changed(adev);
+
+ ret = amdgpu_dpm_pre_set_power_state(adev);
+ if (ret)
+ return;
+
+- if ((0 != amgdpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal)))
+- equal = false;
++ if (adev->powerplay.pp_funcs->check_state_equal) {
++ if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal))
++ equal = false;
++ }
+
+ if (equal)
+ return;
+@@ -1263,7 +1228,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
+ adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
+ adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
+
+- if (adev->pm.funcs->force_performance_level) {
++ if (adev->powerplay.pp_funcs->force_performance_level) {
+ if (adev->pm.dpm.thermal_active) {
+ enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
+ /* force low perf level for thermal */
+@@ -1279,7 +1244,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
+
+ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
+ {
+- if (adev->pp_enabled || adev->pm.funcs->powergate_uvd) {
++ if (adev->powerplay.pp_funcs->powergate_uvd) {
+ /* enable/disable UVD */
+ mutex_lock(&adev->pm.mutex);
+ amdgpu_dpm_powergate_uvd(adev, !enable);
+@@ -1301,7 +1266,7 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
+
+ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
+ {
+- if (adev->pp_enabled || adev->pm.funcs->powergate_vce) {
++ if (adev->powerplay.pp_funcs->powergate_vce) {
+ /* enable/disable VCE */
+ mutex_lock(&adev->pm.mutex);
+ amdgpu_dpm_powergate_vce(adev, !enable);
+@@ -1336,8 +1301,7 @@ void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
+ {
+ int i;
+
+- if (adev->pp_enabled)
+- /* TO DO */
++ if (adev->powerplay.pp_funcs->print_power_state == NULL)
+ return;
+
+ for (i = 0; i < adev->pm.dpm.num_ps; i++)
+@@ -1351,12 +1315,10 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
+
+ if (adev->pm.sysfs_initialized)
+ return 0;
+-
+- if (!adev->pp_enabled) {
+- if (adev->pm.funcs->get_temperature == NULL)
+- return 0;
+- }
+-
++
++ if (adev->powerplay.pp_funcs->get_temperature == NULL)
++ return 0;
++
+ adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
+ DRIVER_NAME, adev,
+ hwmon_groups);
+@@ -1633,8 +1595,8 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
+ return amdgpu_debugfs_pm_info_pp(m, adev);
+ } else {
+ mutex_lock(&adev->pm.mutex);
+- if (adev->pm.funcs->debugfs_print_current_performance_level)
+- adev->pm.funcs->debugfs_print_current_performance_level(adev, m);
++ if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
++ adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
+ else
+ seq_printf(m, "Debugfs support not implemented for this asic\n");
+ mutex_unlock(&adev->pm.mutex);
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+index b0c4db8..5cd5b8e 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+@@ -87,17 +87,20 @@ static int amdgpu_pp_early_init(void *handle)
+ case CHIP_OLAND:
+ case CHIP_HAINAN:
+ amd_pp->ip_funcs = &si_dpm_ip_funcs;
++ amd_pp->pp_funcs = &si_dpm_funcs;
+ break;
+ #endif
+ #ifdef CONFIG_DRM_AMDGPU_CIK
+ case CHIP_BONAIRE:
+ case CHIP_HAWAII:
+ amd_pp->ip_funcs = &ci_dpm_ip_funcs;
++ amd_pp->pp_funcs = &ci_dpm_funcs;
+ break;
+ case CHIP_KABINI:
+ case CHIP_MULLINS:
+ case CHIP_KAVERI:
+ amd_pp->ip_funcs = &kv_dpm_ip_funcs;
++ amd_pp->pp_funcs = &kv_dpm_funcs;
+ break;
+ #endif
+ default:
+diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+index bdf7928..68ce1bd 100644
+--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
++++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+@@ -307,7 +307,6 @@ static int ci_set_power_limit(struct amdgpu_device *adev, u32 n);
+ static int ci_set_overdrive_target_tdp(struct amdgpu_device *adev,
+ u32 target_tdp);
+ static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
+-static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev);
+ static void ci_dpm_set_irq_funcs(struct amdgpu_device *adev);
+
+ static PPSMC_Result amdgpu_ci_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
+@@ -6282,7 +6281,6 @@ static int ci_dpm_early_init(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+- ci_dpm_set_dpm_funcs(adev);
+ ci_dpm_set_irq_funcs(adev);
+
+ return 0;
+@@ -7035,7 +7033,7 @@ const struct amd_ip_funcs ci_dpm_ip_funcs = {
+ .set_powergating_state = ci_dpm_set_powergating_state,
+ };
+
+-static const struct amd_pm_funcs ci_dpm_funcs = {
++const struct amd_pm_funcs ci_dpm_funcs = {
+ .get_temperature = &ci_dpm_get_temp,
+ .pre_set_power_state = &ci_dpm_pre_set_power_state,
+ .set_power_state = &ci_dpm_set_power_state,
+@@ -7067,12 +7065,6 @@ static const struct amd_pm_funcs ci_dpm_funcs = {
+ .read_sensor = ci_dpm_read_sensor,
+ };
+
+-static void ci_dpm_set_dpm_funcs(struct amdgpu_device *adev)
+-{
+- if (adev->pm.funcs == NULL)
+- adev->pm.funcs = &ci_dpm_funcs;
+-}
+-
+ static const struct amdgpu_irq_src_funcs ci_dpm_irq_funcs = {
+ .set = ci_dpm_set_interrupt_state,
+ .process = ci_dpm_process_interrupt,
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
+index b1c8e7b..c7b4349 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
++++ b/drivers/gpu/drm/amd/amdgpu/cik_dpm.h
+@@ -26,5 +26,6 @@
+
+ extern const struct amd_ip_funcs ci_dpm_ip_funcs;
+ extern const struct amd_ip_funcs kv_dpm_ip_funcs;
+-
++extern const struct amd_pm_funcs ci_dpm_funcs;
++extern const struct amd_pm_funcs kv_dpm_funcs;
+ #endif
+diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+index f68d7ab..b57399a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
++++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+@@ -42,7 +42,6 @@
+ #define KV_MINIMUM_ENGINE_CLOCK 800
+ #define SMC_RAM_END 0x40000
+
+-static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev);
+ static void kv_dpm_set_irq_funcs(struct amdgpu_device *adev);
+ static int kv_enable_nb_dpm(struct amdgpu_device *adev,
+ bool enable);
+@@ -2961,7 +2960,6 @@ static int kv_dpm_early_init(void *handle)
+ {
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+- kv_dpm_set_dpm_funcs(adev);
+ kv_dpm_set_irq_funcs(adev);
+
+ return 0;
+@@ -3327,7 +3325,7 @@ const struct amd_ip_funcs kv_dpm_ip_funcs = {
+ .set_powergating_state = kv_dpm_set_powergating_state,
+ };
+
+-static const struct amd_pm_funcs kv_dpm_funcs = {
++const struct amd_pm_funcs kv_dpm_funcs = {
+ .get_temperature = &kv_dpm_get_temp,
+ .pre_set_power_state = &kv_dpm_pre_set_power_state,
+ .set_power_state = &kv_dpm_set_power_state,
+@@ -3345,12 +3343,6 @@ static const struct amd_pm_funcs kv_dpm_funcs = {
+ .read_sensor = &kv_dpm_read_sensor,
+ };
+
+-static void kv_dpm_set_dpm_funcs(struct amdgpu_device *adev)
+-{
+- if (adev->pm.funcs == NULL)
+- adev->pm.funcs = &kv_dpm_funcs;
+-}
+-
+ static const struct amdgpu_irq_src_funcs kv_dpm_irq_funcs = {
+ .set = kv_dpm_set_interrupt_state,
+ .process = kv_dpm_process_interrupt,
+diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+index 6e1240d..ffa2f3f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
++++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+@@ -1848,7 +1848,6 @@ static int si_calculate_sclk_params(struct amdgpu_device *adev,
+
+ static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
+ static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
+-static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
+ static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
+
+ static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
+@@ -7925,7 +7924,6 @@ static int si_dpm_early_init(void *handle)
+
+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+- si_dpm_set_dpm_funcs(adev);
+ si_dpm_set_irq_funcs(adev);
+ return 0;
+ }
+@@ -8043,7 +8041,7 @@ const struct amd_ip_funcs si_dpm_ip_funcs = {
+ .set_powergating_state = si_dpm_set_powergating_state,
+ };
+
+-static const struct amd_pm_funcs si_dpm_funcs = {
++const struct amd_pm_funcs si_dpm_funcs = {
+ .get_temperature = &si_dpm_get_temp,
+ .pre_set_power_state = &si_dpm_pre_set_power_state,
+ .set_power_state = &si_dpm_set_power_state,
+@@ -8064,12 +8062,6 @@ static const struct amd_pm_funcs si_dpm_funcs = {
+ .read_sensor = &si_dpm_read_sensor,
+ };
+
+-static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
+-{
+- if (adev->pm.funcs == NULL)
+- adev->pm.funcs = &si_dpm_funcs;
+-}
+-
+ static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
+ .set = si_dpm_set_interrupt_state,
+ .process = si_dpm_process_interrupt,
+diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.h b/drivers/gpu/drm/amd/amdgpu/si_dpm.h
+index 51ce21c..9fe343d 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.h
++++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.h
+@@ -246,6 +246,7 @@ enum si_display_gap
+ };
+
+ extern const struct amd_ip_funcs si_dpm_ip_funcs;
++extern const struct amd_pm_funcs si_dpm_funcs;
+
+ struct ni_leakage_coeffients
+ {
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-04-24 09:16:43 +0000