diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/1048-drm-amd-powerplay-delete-dead-code-in-powerplay.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/1048-drm-amd-powerplay-delete-dead-code-in-powerplay.patch | 568 |
1 files changed, 568 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/1048-drm-amd-powerplay-delete-dead-code-in-powerplay.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/1048-drm-amd-powerplay-delete-dead-code-in-powerplay.patch new file mode 100644 index 00000000..110a4dcf --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/1048-drm-amd-powerplay-delete-dead-code-in-powerplay.patch @@ -0,0 +1,568 @@ +From 2ba61c26513eb7ff7dea345eaf6405ba1089e0ea Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Mon, 4 Sep 2017 18:22:02 +0800 +Subject: [PATCH 1048/4131] drm/amd/powerplay: delete dead code in powerplay + +delete functiontable related codes + +Change-Id: Ie636d062f1faa127aa2a8ba48fe3a4b7b9f78371 +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +- + drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 3 +- + .../gpu/drm/amd/powerplay/hwmgr/functiontables.c | 161 --------------------- + .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 93 +++--------- + drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 12 -- + drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 3 - + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 - + drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 3 - + drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 49 ------- + 9 files changed, 22 insertions(+), 310 deletions(-) + delete mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +index af5fb85..824fb6f 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +@@ -3,7 +3,7 @@ + # Makefile for the 'hw manager' sub-component of powerplay. + # It provides the hardware management services for the driver. + +-HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \ ++HARDWARE_MGR = hwmgr.o processpptables.o \ + hardwaremanager.o pp_acpi.o cz_hwmgr.o \ + cz_clockpowergating.o pppcielanes.o\ + process_pptables_v1_0.o ppatomctrl.o ppatomfwctrl.o \ +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +index 7efe008..d3b4646 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +@@ -1142,8 +1142,7 @@ static int cz_hwmgr_backend_init(struct pp_hwmgr *hwmgr) + return -ENOMEM; + + hwmgr->backend = data; +- phm_cap_set(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface); ++ + result = cz_initialize_dpm_defaults(hwmgr); + if (result != 0) { + pr_err("cz_initialize_dpm_defaults failed\n"); +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c +deleted file mode 100644 +index bc7d8bd..0000000 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c ++++ /dev/null +@@ -1,161 +0,0 @@ +-/* +- * Copyright 2015 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +-#include <linux/types.h> +-#include <linux/kernel.h> +-#include <linux/slab.h> +-#include "hwmgr.h" +- +-static int phm_run_table(struct pp_hwmgr *hwmgr, +- struct phm_runtime_table_header *rt_table, +- void *input, +- void *output, +- void *temp_storage) +-{ +- int result = 0; +- phm_table_function *function; +- +- if (rt_table->function_list == NULL) { +- pr_debug("this function not implement!\n"); +- return 0; +- } +- +- for (function = rt_table->function_list; NULL != *function; function++) { +- int tmp = (*function)(hwmgr, input, output, temp_storage, result); +- +- if (tmp == PP_Result_TableImmediateExit) +- break; +- if (tmp) { +- if (0 == result) +- result = tmp; +- if (rt_table->exit_error) +- break; +- } +- } +- +- return result; +-} +- +-int phm_dispatch_table(struct pp_hwmgr *hwmgr, +- struct phm_runtime_table_header *rt_table, +- void *input, void *output) +-{ +- int result; +- void *temp_storage; +- +- if (hwmgr == NULL || rt_table == NULL) { +- pr_err("Invalid Parameter!\n"); +- return -EINVAL; +- } +- +- if (0 != rt_table->storage_size) { +- temp_storage = kzalloc(rt_table->storage_size, GFP_KERNEL); +- if (temp_storage == NULL) { +- pr_err("Could not allocate table temporary storage\n"); +- return -ENOMEM; +- } +- } else { +- temp_storage = NULL; +- } +- +- result = phm_run_table(hwmgr, rt_table, input, output, temp_storage); +- +- kfree(temp_storage); +- +- return result; +-} +- +-int phm_construct_table(struct pp_hwmgr *hwmgr, +- const struct phm_master_table_header *master_table, +- struct phm_runtime_table_header *rt_table) +-{ +- uint32_t function_count = 0; +- const struct phm_master_table_item *table_item; +- uint32_t size; +- phm_table_function *run_time_list; +- phm_table_function *rtf; +- +- if (hwmgr == NULL || master_table == NULL || rt_table == NULL) { +- pr_err("Invalid Parameter!\n"); +- return -EINVAL; +- } +- +- for (table_item = master_table->master_list; +- NULL != table_item->tableFunction; table_item++) { +- if ((NULL == table_item->isFunctionNeededInRuntimeTable) || +- (table_item->isFunctionNeededInRuntimeTable(hwmgr))) +- function_count++; +- } +- +- size = (function_count + 1) * sizeof(phm_table_function); +- run_time_list = kzalloc(size, GFP_KERNEL); +- +- if (NULL == run_time_list) +- return -ENOMEM; +- +- rtf = run_time_list; +- for (table_item = master_table->master_list; +- NULL != table_item->tableFunction; table_item++) { +- if ((rtf - run_time_list) > function_count) { +- pr_err("Check function results have changed\n"); +- kfree(run_time_list); +- return -EINVAL; +- } +- +- if ((NULL == table_item->isFunctionNeededInRuntimeTable) || +- (table_item->isFunctionNeededInRuntimeTable(hwmgr))) { +- *(rtf++) = table_item->tableFunction; +- } +- } +- +- if ((rtf - run_time_list) > function_count) { +- pr_err("Check function results have changed\n"); +- kfree(run_time_list); +- return -EINVAL; +- } +- +- *rtf = NULL; +- rt_table->function_list = run_time_list; +- rt_table->exit_error = (0 != (master_table->flags & PHM_MasterTableFlag_ExitOnError)); +- rt_table->storage_size = master_table->storage_size; +- return 0; +-} +- +-int phm_destroy_table(struct pp_hwmgr *hwmgr, +- struct phm_runtime_table_header *rt_table) +-{ +- if (hwmgr == NULL || rt_table == NULL) { +- pr_err("Invalid Parameter\n"); +- return -EINVAL; +- } +- +- if (NULL == rt_table->function_list) +- return 0; +- +- kfree(rt_table->function_list); +- +- rt_table->function_list = NULL; +- rt_table->storage_size = 0; +- rt_table->exit_error = false; +- +- return 0; +-} +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c +index a3991c0..fa4fbc2 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c +@@ -36,29 +36,12 @@ + return -EINVAL; \ + } while (0) + +-bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr) +-{ +- return hwmgr->block_hw_access; +-} +- +-int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block) +-{ +- hwmgr->block_hw_access = block; +- return 0; +-} +- + int phm_setup_asic(struct pp_hwmgr *hwmgr) + { + PHM_FUNC_CHECK(hwmgr); + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface)) { +- if (NULL != hwmgr->hwmgr_func->asic_setup) +- return hwmgr->hwmgr_func->asic_setup(hwmgr); +- } else { +- return phm_dispatch_table(hwmgr, &(hwmgr->setup_asic), +- NULL, NULL); +- } ++ if (NULL != hwmgr->hwmgr_func->asic_setup) ++ return hwmgr->hwmgr_func->asic_setup(hwmgr); + + return 0; + } +@@ -67,14 +50,8 @@ int phm_power_down_asic(struct pp_hwmgr *hwmgr) + { + PHM_FUNC_CHECK(hwmgr); + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface)) { +- if (NULL != hwmgr->hwmgr_func->power_off_asic) +- return hwmgr->hwmgr_func->power_off_asic(hwmgr); +- } else { +- return phm_dispatch_table(hwmgr, &(hwmgr->power_down_asic), +- NULL, NULL); +- } ++ if (NULL != hwmgr->hwmgr_func->power_off_asic) ++ return hwmgr->hwmgr_func->power_off_asic(hwmgr); + + return 0; + } +@@ -90,13 +67,8 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr, + states.pcurrent_state = pcurrent_state; + states.pnew_state = pnew_power_state; + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface)) { +- if (NULL != hwmgr->hwmgr_func->power_state_set) +- return hwmgr->hwmgr_func->power_state_set(hwmgr, &states); +- } else { +- return phm_dispatch_table(hwmgr, &(hwmgr->set_power_state), &states, NULL); +- } ++ if (NULL != hwmgr->hwmgr_func->power_state_set) ++ return hwmgr->hwmgr_func->power_state_set(hwmgr, &states); + + return 0; + } +@@ -107,15 +79,8 @@ int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr) + bool enabled; + PHM_FUNC_CHECK(hwmgr); + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface)) { +- if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable) +- ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); +- } else { +- ret = phm_dispatch_table(hwmgr, +- &(hwmgr->enable_dynamic_state_management), +- NULL, NULL); +- } ++ if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable) ++ ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); + + enabled = ret == 0; + +@@ -131,15 +96,8 @@ int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr) + + PHM_FUNC_CHECK(hwmgr); + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface)) { +- if (hwmgr->hwmgr_func->dynamic_state_management_disable) +- ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr); +- } else { +- ret = phm_dispatch_table(hwmgr, +- &(hwmgr->disable_dynamic_state_management), +- NULL, NULL); +- } ++ if (hwmgr->hwmgr_func->dynamic_state_management_disable) ++ ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr); + + enabled = ret == 0 ? false : true; + +@@ -219,13 +177,9 @@ int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr) + { + PHM_FUNC_CHECK(hwmgr); + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface)) { +- if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating) +- return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr); +- } else { +- return phm_dispatch_table(hwmgr, &(hwmgr->enable_clock_power_gatings), NULL, NULL); +- } ++ if (NULL != hwmgr->hwmgr_func->enable_clock_power_gating) ++ return hwmgr->hwmgr_func->enable_clock_power_gating(hwmgr); ++ + return 0; + } + +@@ -233,11 +187,9 @@ int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr) + { + PHM_FUNC_CHECK(hwmgr); + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface)) { +- if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating) +- return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr); +- } ++ if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating) ++ return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr); ++ + return 0; + } + +@@ -246,12 +198,9 @@ int phm_display_configuration_changed(struct pp_hwmgr *hwmgr) + { + PHM_FUNC_CHECK(hwmgr); + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface)) { +- if (NULL != hwmgr->hwmgr_func->display_config_changed) +- hwmgr->hwmgr_func->display_config_changed(hwmgr); +- } else +- return phm_dispatch_table(hwmgr, &hwmgr->display_configuration_changed, NULL, NULL); ++ if (NULL != hwmgr->hwmgr_func->display_config_changed) ++ hwmgr->hwmgr_func->display_config_changed(hwmgr); ++ + return 0; + } + +@@ -259,9 +208,7 @@ int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) + { + PHM_FUNC_CHECK(hwmgr); + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface)) +- if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment) ++ if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment) + hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr); + + return 0; +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +index 387d0b6..e3bf69c 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +@@ -852,10 +852,6 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr) + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_AutomaticDCTransition); + +- phm_cap_set(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface); +- +- + if (hwmgr->chip_id != CHIP_POLARIS10) + phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SPLLShutdownSupport); +@@ -882,9 +878,6 @@ int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr) + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_TCPRamping); + +- phm_cap_set(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface); +- + return 0; + } + +@@ -904,9 +897,6 @@ int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr) + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_VCEPowerGating); + +- phm_cap_set(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface); +- + return 0; + } + +@@ -921,8 +911,6 @@ int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr) + phm_cap_unset(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_TCPRamping); + phm_cap_set(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface); +- phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EVV); + return 0; + } +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +index 5d170b2..947e24c 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +@@ -456,9 +456,6 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr) + + hwmgr->backend = data; + +- phm_cap_set(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface); +- + result = rv_initialize_dpm_defaults(hwmgr); + if (result != 0) { + pr_err("rv_initialize_dpm_defaults failed\n"); +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index 99a233c..ece7ee7 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -3857,9 +3857,6 @@ static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f + hwmgr->thermal_controller. + advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; + +- if (phm_is_hw_access_blocked(hwmgr)) +- return 0; +- + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm); + } +@@ -3962,9 +3959,6 @@ static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_f + hwmgr->thermal_controller. + advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; + +- if (phm_is_hw_access_blocked(hwmgr)) +- return 0; +- + return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm); + } +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index c60b80059..b7bf18c 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -201,9 +201,6 @@ static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr) + PHM_PlatformCaps_ControlVDDCI); + + phm_cap_set(hwmgr->platform_descriptor.platformCaps, +- PHM_PlatformCaps_TablelessHardwareInterface); +- +- phm_cap_set(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_EnableSMU7ThermalManagement); + + sys_info.size = sizeof(struct cgs_system_info); +diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +index 831add4..2a10d81 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +@@ -109,10 +109,6 @@ enum PHM_BackEnd_Magic { + #define PHM_PCIE_POWERGATING_TARGET_PLLCASCADE 2 + #define PHM_PCIE_POWERGATING_TARGET_PHY 3 + +-typedef int (*phm_table_function)(struct pp_hwmgr *hwmgr, void *input, +- void *output, void *storage, int result); +- +-typedef bool (*phm_check_function)(struct pp_hwmgr *hwmgr); + + struct phm_set_power_state_input { + const struct pp_hw_power_state *pcurrent_state; +@@ -149,30 +145,6 @@ struct phm_gfx_arbiter { + uint32_t fclk; + }; + +-/* Entries in the master tables */ +-struct phm_master_table_item { +- phm_check_function isFunctionNeededInRuntimeTable; +- phm_table_function tableFunction; +-}; +- +-enum phm_master_table_flag { +- PHM_MasterTableFlag_None = 0, +- PHM_MasterTableFlag_ExitOnError = 1, +-}; +- +-/* The header of the master tables */ +-struct phm_master_table_header { +- uint32_t storage_size; +- uint32_t flags; +- const struct phm_master_table_item *master_list; +-}; +- +-struct phm_runtime_table_header { +- uint32_t storage_size; +- bool exit_error; +- phm_table_function *function_list; +-}; +- + struct phm_clock_array { + uint32_t count; + uint32_t values[1]; +@@ -216,19 +188,6 @@ struct phm_phase_shedding_limits_record { + uint32_t Mclk; + }; + +- +-extern int phm_dispatch_table(struct pp_hwmgr *hwmgr, +- struct phm_runtime_table_header *rt_table, +- void *input, void *output); +- +-extern int phm_construct_table(struct pp_hwmgr *hwmgr, +- const struct phm_master_table_header *master_table, +- struct phm_runtime_table_header *rt_table); +- +-extern int phm_destroy_table(struct pp_hwmgr *hwmgr, +- struct phm_runtime_table_header *rt_table); +- +- + struct phm_uvd_clock_voltage_dependency_record { + uint32_t vclk; + uint32_t dclk; +@@ -749,7 +708,6 @@ struct pp_hwmgr { + enum amd_dpm_forced_level dpm_level; + enum amd_dpm_forced_level saved_dpm_level; + enum amd_dpm_forced_level request_dpm_level; +- bool block_hw_access; + struct phm_gfx_arbiter gfx_arbiter; + struct phm_acp_arbiter acp_arbiter; + struct phm_uvd_arbiter uvd_arbiter; +@@ -760,13 +718,6 @@ struct pp_hwmgr { + void *backend; + enum PP_DAL_POWERLEVEL dal_power_level; + struct phm_dynamic_state_info dyn_state; +- struct phm_runtime_table_header setup_asic; +- struct phm_runtime_table_header power_down_asic; +- struct phm_runtime_table_header disable_dynamic_state_management; +- struct phm_runtime_table_header enable_dynamic_state_management; +- struct phm_runtime_table_header set_power_state; +- struct phm_runtime_table_header enable_clock_power_gatings; +- struct phm_runtime_table_header display_configuration_changed; + const struct pp_hwmgr_func *hwmgr_func; + const struct pp_table_func *pptable_func; + struct pp_power_state *ps; +-- +2.7.4 + |