diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/1024-drm-amd-display-only-polling-VSync-Phase-within-VSyn.patch')
-rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/1024-drm-amd-display-only-polling-VSync-Phase-within-VSyn.patch | 149 |
1 files changed, 149 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/1024-drm-amd-display-only-polling-VSync-Phase-within-VSyn.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/1024-drm-amd-display-only-polling-VSync-Phase-within-VSyn.patch new file mode 100644 index 00000000..5f79ea2b --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/1024-drm-amd-display-only-polling-VSync-Phase-within-VSyn.patch @@ -0,0 +1,149 @@ +From 83c1c0bfced77a141d90d8f81375e5422be344bf Mon Sep 17 00:00:00 2001 +From: Charlene Liu <charlene.liu@amd.com> +Date: Mon, 28 Aug 2017 16:28:34 -0400 +Subject: [PATCH 1024/4131] drm/amd/display: only polling VSync Phase within + VSync peroroid + +Change-Id: I9b40c7217b030f0d21ee0f4d3f871e872ba8332a +Signed-off-by: Charlene Liu <charlene.liu@amd.com> +Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 ++-- + drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 ++-- + drivers/gpu/drm/amd/display/dc/dc.h | 2 +- + drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 27 +++++++++++++----------- + drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h | 2 +- + 5 files changed, 21 insertions(+), 18 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +index b95b58d..cea8daf 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +@@ -1862,13 +1862,13 @@ bool dc_link_set_abm_disable(const struct dc_link *link) + } + + +-bool dc_link_set_psr_enable(const struct dc_link *link, bool enable) ++bool dc_link_set_psr_enable(const struct dc_link *link, bool enable, bool wait) + { + struct dc *core_dc = link->ctx->dc; + struct dmcu *dmcu = core_dc->res_pool->dmcu; + + if (dmcu != NULL && link->psr_enabled) +- dmcu->funcs->set_psr_enable(dmcu, enable); ++ dmcu->funcs->set_psr_enable(dmcu, enable, wait); + + return true; + } +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +index 5f2b52e..527cc04 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +@@ -1653,8 +1653,8 @@ static bool handle_hpd_irq_psr_sink(const struct dc_link *link) + sizeof(psr_error_status.raw)); + + /* PSR error, disable and re-enable PSR */ +- dc_link_set_psr_enable(link, false); +- dc_link_set_psr_enable(link, true); ++ dc_link_set_psr_enable(link, false, true); ++ dc_link_set_psr_enable(link, true, true); + + return true; + } else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS == +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index ff636cc..d6d7f34 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -886,7 +886,7 @@ struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); + bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, + uint32_t frame_ramp, const struct dc_stream_state *stream); + +-bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); ++bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable, bool wait); + + bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +index efcdb2b..313f61b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +@@ -103,7 +103,7 @@ static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) + REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); + } + +-static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable) ++static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) + { + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + unsigned int dmcu_max_retry_on_wait_reg_ready = 801; +@@ -127,17 +127,18 @@ static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable) + + /* notifyDMCUMsg */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); +- +- for (retryCount = 0; retryCount <= 100; retryCount++) { +- dce_get_dmcu_psr_state(dmcu, &psr_state); +- if (enable) { +- if (psr_state != 0) +- break; +- } else { +- if (psr_state == 0) +- break; ++ if (wait == true) { ++ for (retryCount = 0; retryCount <= 100; retryCount++) { ++ dce_get_dmcu_psr_state(dmcu, &psr_state); ++ if (enable) { ++ if (psr_state != 0) ++ break; ++ } else { ++ if (psr_state == 0) ++ break; ++ } ++ dm_delay_in_microseconds(dmcu->ctx, 10); + } +- dm_delay_in_microseconds(dmcu->ctx, 10); + } + } + +@@ -338,7 +339,7 @@ static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) + REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); + } + +-static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable) ++static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait) + { + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + unsigned int dmcu_max_retry_on_wait_reg_ready = 801; +@@ -367,6 +368,7 @@ static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable) + * Exit PSR may need to wait 1-2 frames to power up. Timeout after at + * least a few frames. Should never hit the max retry assert below. + */ ++ if (wait == true) { + for (retryCount = 0; retryCount <= 1000; retryCount++) { + dcn10_get_dmcu_psr_state(dmcu, &psr_state); + if (enable) { +@@ -381,6 +383,7 @@ static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable) + + /* assert if max retry hit */ + ASSERT(retryCount <= 1000); ++ } + } + + static void dcn10_dmcu_setup_psr(struct dmcu *dmcu, +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h +index e34b259..0574c29 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h +@@ -37,7 +37,7 @@ struct dmcu_funcs { + unsigned int start_offset, + const char *src, + unsigned int bytes); +- void (*set_psr_enable)(struct dmcu *dmcu, bool enable); ++ void (*set_psr_enable)(struct dmcu *dmcu, bool enable, bool wait); + void (*setup_psr)(struct dmcu *dmcu, + struct dc_link *link, + struct psr_context *psr_context); +-- +2.7.4 + |