aboutsummaryrefslogtreecommitdiffstats
path: root/common/recipes-kernel/linux/linux-yocto-4.14.71/0918-drm-amdgpu-move-amdgpu_cs_sysvm_access_required-into.patch
diff options
context:
space:
mode:
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0918-drm-amdgpu-move-amdgpu_cs_sysvm_access_required-into.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/0918-drm-amdgpu-move-amdgpu_cs_sysvm_access_required-into.patch237
1 files changed, 237 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0918-drm-amdgpu-move-amdgpu_cs_sysvm_access_required-into.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0918-drm-amdgpu-move-amdgpu_cs_sysvm_access_required-into.patch
new file mode 100644
index 00000000..04fba8bb
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0918-drm-amdgpu-move-amdgpu_cs_sysvm_access_required-into.patch
@@ -0,0 +1,237 @@
+From 85c632dd1887ce61fffff1201ab878fdefd866c0 Mon Sep 17 00:00:00 2001
+From: Christian Koenig <christian.koenig@amd.com>
+Date: Wed, 6 Sep 2017 16:15:28 +0200
+Subject: [PATCH 0918/4131] drm/amdgpu: move amdgpu_cs_sysvm_access_required
+ into find_mapping
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+When we need to find the mapping we need sysvm access anyway.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Acked-by: Leo Liu <leo.liu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 ++---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 64 ++++++++++++---------------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 16 ++++-----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 11 +++---
+ 4 files changed, 36 insertions(+), 63 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index bdee4b0..3c7a9bf 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -183,6 +183,7 @@ struct amdgpu_job;
+ struct amdgpu_irq_src;
+ struct amdgpu_fpriv;
+ struct amdgpu_mn;
++struct amdgpu_bo_va_mapping;
+
+ enum amdgpu_cp_irq {
+ AMDGPU_CP_IRQ_GFX_EOP = 0,
+@@ -1961,10 +1962,9 @@ static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
+ static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
+ #endif
+
+-struct amdgpu_bo_va_mapping *
+-amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
+- uint64_t addr, struct amdgpu_bo **bo);
+-int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
++int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
++ uint64_t addr, struct amdgpu_bo **bo,
++ struct amdgpu_bo_va_mapping **mapping);
+
+ #if defined(CONFIG_DRM_AMD_DC)
+ int amdgpu_dm_display_resume(struct amdgpu_device *adev );
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+index 091b4eb..b6e536a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+@@ -934,11 +934,11 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
+ uint64_t offset;
+ uint8_t *kptr;
+
+- m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
+- &aobj);
+- if (!aobj) {
++ r = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
++ &aobj, &m);
++ if (r) {
+ DRM_ERROR("IB va_start is invalid\n");
+- return -EINVAL;
++ return r;
+ }
+
+ if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
+@@ -1488,15 +1488,16 @@ int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
+ * virtual memory address. Returns allocation structure when found, NULL
+ * otherwise.
+ */
+-struct amdgpu_bo_va_mapping *
+-amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
+- uint64_t addr, struct amdgpu_bo **bo)
++int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
++ uint64_t addr, struct amdgpu_bo **bo,
++ struct amdgpu_bo_va_mapping **map)
+ {
+ struct amdgpu_bo_va_mapping *mapping;
+ unsigned i;
++ int r;
+
+ if (!parser->bo_list)
+- return NULL;
++ return 0;
+
+ addr /= AMDGPU_GPU_PAGE_SIZE;
+
+@@ -1513,7 +1514,8 @@ amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
+ continue;
+
+ *bo = lobj->bo_va->base.bo;
+- return mapping;
++ *map = mapping;
++ goto found;
+ }
+
+ list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
+@@ -1522,44 +1524,22 @@ amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
+ continue;
+
+ *bo = lobj->bo_va->base.bo;
+- return mapping;
++ *map = mapping;
++ goto found;
+ }
+ }
+
+- return NULL;
+-}
++ return -EINVAL;
+
+-/**
+- * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM
+- *
+- * @parser: command submission parser context
+- *
+- * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM.
+- */
+-int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser)
+-{
+- unsigned i;
+- int r;
++found:
++ r = amdgpu_ttm_bind(&(*bo)->tbo, &(*bo)->tbo.mem);
++ if (unlikely(r))
++ return r;
+
+- if (!parser->bo_list)
++ if ((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
+ return 0;
+
+- for (i = 0; i < parser->bo_list->num_entries; i++) {
+- struct amdgpu_bo *bo = parser->bo_list->array[i].robj;
+-
+- r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
+- if (unlikely(r))
+- return r;
+-
+- if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
+- continue;
+-
+- bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+- amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains);
+- r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
+- if (unlikely(r))
+- return r;
+- }
+-
+- return 0;
++ (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
++ amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains);
++ return ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, false, false);
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+index 17deca0..2a01a64 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+@@ -413,10 +413,10 @@ static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx)
+ uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
+ int r = 0;
+
+- mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
+- if (mapping == NULL) {
++ r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
++ if (r) {
+ DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
+- return -EINVAL;
++ return r;
+ }
+
+ if (!ctx->parser->adev->uvd.address_64_bit) {
+@@ -740,10 +740,10 @@ static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx)
+ uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
+ int r;
+
+- mapping = amdgpu_cs_find_mapping(ctx->parser, addr, &bo);
+- if (mapping == NULL) {
++ r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
++ if (r) {
+ DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
+- return -EINVAL;
++ return r;
+ }
+
+ start = amdgpu_bo_gpu_offset(bo);
+@@ -920,10 +920,6 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx)
+ return -EINVAL;
+ }
+
+- r = amdgpu_cs_sysvm_access_required(parser);
+- if (r)
+- return r;
+-
+ ctx.parser = parser;
+ ctx.buf_sizes = buf_sizes;
+ ctx.ib_idx = ib_idx;
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+index 9fc3d38..2918de2 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+@@ -559,6 +559,7 @@ static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
+ struct amdgpu_bo_va_mapping *mapping;
+ struct amdgpu_bo *bo;
+ uint64_t addr;
++ int r;
+
+ if (index == 0xffffffff)
+ index = 0;
+@@ -567,11 +568,11 @@ static int amdgpu_vce_cs_reloc(struct amdgpu_cs_parser *p, uint32_t ib_idx,
+ ((uint64_t)amdgpu_get_ib_value(p, ib_idx, hi)) << 32;
+ addr += ((uint64_t)size) * ((uint64_t)index);
+
+- mapping = amdgpu_cs_find_mapping(p, addr, &bo);
+- if (mapping == NULL) {
++ r = amdgpu_cs_find_mapping(p, addr, &bo, &mapping);
++ if (r) {
+ DRM_ERROR("Can't find BO for addr 0x%010Lx %d %d %d %d\n",
+ addr, lo, hi, size, index);
+- return -EINVAL;
++ return r;
+ }
+
+ if ((addr + (uint64_t)size) >
+@@ -652,10 +653,6 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
+ p->job->vm = NULL;
+ ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
+
+- r = amdgpu_cs_sysvm_access_required(p);
+- if (r)
+- return r;
+-
+ while (idx < ib->length_dw) {
+ uint32_t len = amdgpu_get_ib_value(p, ib_idx, idx);
+ uint32_t cmd = amdgpu_get_ib_value(p, ib_idx, idx + 1);
+--
+2.7.4
+