aboutsummaryrefslogtreecommitdiffstats
path: root/common/recipes-kernel/linux/linux-yocto-4.14.71/0909-drm-amd-powerplay-set-uvd-vce-nb-mclk-level-as-UMD-P.patch
diff options
context:
space:
mode:
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0909-drm-amd-powerplay-set-uvd-vce-nb-mclk-level-as-UMD-P.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/0909-drm-amd-powerplay-set-uvd-vce-nb-mclk-level-as-UMD-P.patch53
1 files changed, 53 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0909-drm-amd-powerplay-set-uvd-vce-nb-mclk-level-as-UMD-P.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0909-drm-amd-powerplay-set-uvd-vce-nb-mclk-level-as-UMD-P.patch
new file mode 100644
index 00000000..bae0dd3f
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0909-drm-amd-powerplay-set-uvd-vce-nb-mclk-level-as-UMD-P.patch
@@ -0,0 +1,53 @@
+From 221ff4e1d9309c7d176310d6beb5cd25f4bea414 Mon Sep 17 00:00:00 2001
+From: Rex Zhu <Rex.Zhu@amd.com>
+Date: Tue, 29 Aug 2017 17:07:38 +0800
+Subject: [PATCH 0909/4131] drm/amd/powerplay: set uvd/vce/nb/mclk level as UMD
+ P-state required
+
+Change-Id: I5391ef747de07437609a6bdcc7cfba29d82d2579
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
+---
+ drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+index a301003..7f3b24f 100644
+--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+@@ -1138,7 +1138,11 @@ static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
+
+ cz_ps->action = cz_current_ps->action;
+
+- if (!force_high && (cz_ps->action == FORCE_HIGH))
++ if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
++ cz_nbdpm_pstate_enable_disable(hwmgr, false, false);
++ else if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD)
++ cz_nbdpm_pstate_enable_disable(hwmgr, false, true);
++ else if (!force_high && (cz_ps->action == FORCE_HIGH))
+ cz_ps->action = CANCEL_FORCE_HIGH;
+ else if (force_high && (cz_ps->action != FORCE_HIGH))
+ cz_ps->action = FORCE_HIGH;
+@@ -1374,7 +1378,8 @@ int cz_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
+ if (!bgate) {
+ /* Stable Pstate is enabled and we need to set the UVD DPM to highest level */
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+- PHM_PlatformCaps_StablePState)) {
++ PHM_PlatformCaps_StablePState)
++ || hwmgr->en_umd_pstate) {
+ cz_hwmgr->uvd_dpm.hard_min_clk =
+ ptable->entries[ptable->count - 1].vclk;
+
+@@ -1403,7 +1408,8 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
+
+ /* Stable Pstate is enabled and we need to set the VCE DPM to highest level */
+ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
+- PHM_PlatformCaps_StablePState)) {
++ PHM_PlatformCaps_StablePState)
++ || hwmgr->en_umd_pstate) {
+ cz_hwmgr->vce_dpm.hard_min_clk =
+ ptable->entries[ptable->count - 1].ecclk;
+
+--
+2.7.4
+