diff options
Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0731-drm-amd-display-Implement-tmz-surface.patch')
| -rw-r--r-- | common/recipes-kernel/linux/linux-yocto-4.14.71/0731-drm-amd-display-Implement-tmz-surface.patch | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0731-drm-amd-display-Implement-tmz-surface.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0731-drm-amd-display-Implement-tmz-surface.patch new file mode 100644 index 00000000..484ab6ff --- /dev/null +++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0731-drm-amd-display-Implement-tmz-surface.patch @@ -0,0 +1,85 @@ +From 875884ccb32a9c7620c50810200e9e0f715f0618 Mon Sep 17 00:00:00 2001 +From: Yongqiang Sun <yongqiang.sun@amd.com> +Date: Tue, 1 Aug 2017 16:54:48 -0400 +Subject: [PATCH 0731/4131] drm/amd/display: Implement tmz surface. + +Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 1 + + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 10 ++++++++++ + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 2 ++ + 3 files changed, 13 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +index 3c0b473..778bd55 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h ++++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +@@ -66,6 +66,7 @@ enum dc_plane_addr_type { + + struct dc_plane_address { + enum dc_plane_addr_type type; ++ bool tmz_surface; + union { + struct{ + PHYSICAL_ADDRESS_LOC addr; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +index 76879f5..0d40fa7 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +@@ -266,6 +266,9 @@ static bool min10_program_surface_flip_and_addr( + if (address->grph.addr.quad_part == 0) + break; + ++ REG_UPDATE(DCSURF_SURFACE_CONTROL, ++ PRIMARY_SURFACE_TMZ, address->tmz_surface); ++ + if (address->grph.meta_addr.quad_part != 0) { + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH, +@@ -289,6 +292,9 @@ static bool min10_program_surface_flip_and_addr( + || address->video_progressive.chroma_addr.quad_part == 0) + break; + ++ REG_UPDATE(DCSURF_SURFACE_CONTROL, ++ PRIMARY_SURFACE_TMZ, address->tmz_surface); ++ + if (address->video_progressive.luma_meta_addr.quad_part != 0) { + REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0, + PRIMARY_META_SURFACE_ADDRESS_HIGH_C, +@@ -328,6 +334,10 @@ static bool min10_program_surface_flip_and_addr( + break; + if (address->grph_stereo.right_addr.quad_part == 0) + break; ++ ++ REG_UPDATE(DCSURF_SURFACE_CONTROL, ++ PRIMARY_SURFACE_TMZ, address->tmz_surface); ++ + if (address->grph_stereo.right_meta_addr.quad_part != 0) { + + REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h +index 4f4e2c0..e2eba25 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h +@@ -303,6 +303,7 @@ struct dcn_mi_registers { + MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\ + MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\ + MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\ ++ MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_TMZ, mask_sh),\ + MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\ + MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\ + MI_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\ +@@ -453,6 +454,7 @@ struct dcn_mi_registers { + type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\ + type SURFACE_EARLIEST_INUSE_ADDRESS_C;\ + type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\ ++ type PRIMARY_SURFACE_TMZ;\ + type PRIMARY_SURFACE_DCC_EN;\ + type PRIMARY_SURFACE_DCC_IND_64B_BLK;\ + type DET_BUF_PLANE1_BASE_ADDRESS;\ +-- +2.7.4 + |