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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0729-drm-amd-display-update-predefined-latency-for-Rv1_F0.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/0729-drm-amd-display-update-predefined-latency-for-Rv1_F0.patch60
1 files changed, 60 insertions, 0 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0729-drm-amd-display-update-predefined-latency-for-Rv1_F0.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0729-drm-amd-display-update-predefined-latency-for-Rv1_F0.patch
new file mode 100644
index 00000000..8f3ff3a1
--- /dev/null
+++ b/common/recipes-kernel/linux/linux-yocto-4.14.71/0729-drm-amd-display-update-predefined-latency-for-Rv1_F0.patch
@@ -0,0 +1,60 @@
+From 1aa0618a7216b875fa7ddac97209d488d4c36ebc Mon Sep 17 00:00:00 2001
+From: Charlene Liu <charlene.liu@amd.com>
+Date: Tue, 1 Aug 2017 13:23:56 -0400
+Subject: [PATCH 0729/4131] drm/amd/display: update predefined latency for
+ Rv1_F0
+
+Signed-off-by: Charlene Liu <charlene.liu@amd.com>
+Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
+Acked-by: Harry Wentland <Harry.Wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 10 ++++++++++
+ drivers/gpu/drm/amd/display/include/dal_asic_id.h | 3 +++
+ 2 files changed, 13 insertions(+)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index ff2dcb7..6006fb4 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -1323,6 +1323,13 @@ static bool construct(
+ dc->dcn_ip = dcn10_ip_defaults;
+ dc->dcn_soc = dcn10_soc_defaults;
+
++ if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
++ dc->dcn_soc.urgent_latency = 3;
++ dc->public.debug.disable_dmcu = true;
++ dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 = 41.60f;
++ }
++
++
+ dc->dcn_soc.number_of_channels = dc->ctx->asic_id.vram_width / ddr4_dram_width;
+ ASSERT(dc->dcn_soc.number_of_channels < 3);
+ if (dc->dcn_soc.number_of_channels == 0)/*old sbios bug*/
+@@ -1333,6 +1340,9 @@ static bool construct(
+ dc->dcn_soc.fabric_and_dram_bandwidth_vnom0p8 = 17.066f;
+ dc->dcn_soc.fabric_and_dram_bandwidth_vmid0p72 = 14.933f;
+ dc->dcn_soc.fabric_and_dram_bandwidth_vmin0p65 = 12.8f;
++ if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
++ dc->dcn_soc.fabric_and_dram_bandwidth_vmax0p9 = 20.80f;
++ }
+ }
+
+ if (!dc->public.debug.disable_pplib_clock_request)
+diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+index af9fa66..14e3146 100644
+--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
++++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+@@ -115,6 +115,9 @@
+ #define RAVEN_UNKNOWN 0xFF
+
+ #define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
++#define RAVEN1_F0 0xF0
++#define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
++
+
+ #define FAMILY_RV 142 /* DCN 1*/
+
+--
+2.7.4
+