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Diffstat (limited to 'common/recipes-kernel/linux/linux-yocto-4.14.71/0717-drm-amd-display-Move-TG-to-stream_res.patch')
-rw-r--r--common/recipes-kernel/linux/linux-yocto-4.14.71/0717-drm-amd-display-Move-TG-to-stream_res.patch799
1 files changed, 0 insertions, 799 deletions
diff --git a/common/recipes-kernel/linux/linux-yocto-4.14.71/0717-drm-amd-display-Move-TG-to-stream_res.patch b/common/recipes-kernel/linux/linux-yocto-4.14.71/0717-drm-amd-display-Move-TG-to-stream_res.patch
deleted file mode 100644
index 13b49ba4..00000000
--- a/common/recipes-kernel/linux/linux-yocto-4.14.71/0717-drm-amd-display-Move-TG-to-stream_res.patch
+++ /dev/null
@@ -1,799 +0,0 @@
-From 19bcc44d9d273e469c9c8c4b6eee688c1bedfddf Mon Sep 17 00:00:00 2001
-From: Harry Wentland <harry.wentland@amd.com>
-Date: Sun, 30 Jul 2017 13:59:26 -0400
-Subject: [PATCH 0717/4131] drm/amd/display: Move TG to stream_res
-
-find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
--o -name "*.cpp" -o -name "*.hpp" | \
-xargs sed -i 's/pipes->tg/pipes->stream_res\.tg/g'
-
-find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
--o -name "*.cpp" -o -name "*.hpp" | \
-xargs sed -i 's/ctx->tg->/ctx->stream_res\.tg->/g'
-
-find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
--o -name "*.cpp" -o -name "*.hpp" | \
-xargs sed -i 's/pipe->tg/pipe->stream_res\.tg/g'
-
-find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
--o -name "*.cpp" -o -name "*.hpp" | \
-xargs sed -i 's/pipe_ctx->tg/pipe_ctx->stream_res\.tg/g'
-
-find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
--o -name "*.cpp" -o -name "*.hpp" | \
-xargs sed -i \
-'s/pipe_ctx\[pipe_offset\]\.tg/pipe_ctx\[pipe_offset\]\.stream_res\.tg/g'
-
-find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
--o -name "*.cpp" -o -name "*.hpp" | \
-xargs sed -i
-'s/grouped_pipes\[i\]->tg/grouped_pipes\[i\]->stream_^Cs\.tg/g'
-
-find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
--o -name "*.cpp" -o -name "*.hpp" | \
-xargs sed -i
-'s/grouped_pipes\[0\]->tg/grouped_pipes\[0\]->stream_res\.tg/g'
-
-find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
--o -name "*.cpp" -o -name "*.hpp" | \
-xargs sed -i
-'s/grouped_pipes\[1\]->tg/grouped_pipes\[1\]->stream_res\.tg/g'
-
-find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
--o -name "*.cpp" -o -name "*.hpp" | \
-xargs sed -i 's/pipe_ctx\[i\]->tg/pipe_ctx\[i\]->stream_res\.tg/g'
-
-find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
--o -name "*.cpp" -o -name "*.hpp" | \
-xargs sed -i 's/pipe_ctx_old->tg/pipe_ctx_old->stream_res\.tg/g'
-
-find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
--o -name "*.cpp" -o -name "*.hpp" | \
-xargs sed -i 's/pipe_set\[j\]->tg/pipe_set\[j\]->stream_res\.tg/g'
-
-find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \
--o -name "*.cpp" -o -name "*.hpp" | \
-xargs sed -i 's/pipe_ctx\[i\]\.tg/pipe_ctx\[i\]\.stream_res\.tg/g'
-
-Signed-off-by: Harry Wentland <harry.wentland@amd.com>
-Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
-Acked-by: Harry Wentland <Harry.Wentland@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
----
- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +-
- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 4 +-
- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +-
- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 4 +-
- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 8 +-
- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 +-
- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 2 +-
- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 64 +++++++--------
- .../drm/amd/display/dc/dce110/dce110_resource.c | 12 +--
- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 96 +++++++++++-----------
- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +-
- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 +-
- .../amd/display/dc/irq/dce110/irq_service_dce110.c | 2 +-
- 13 files changed, 105 insertions(+), 106 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
-index 507732e..61c2a21 100644
---- a/drivers/gpu/drm/amd/display/dc/core/dc.c
-+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
-@@ -846,7 +846,7 @@ static void program_timing_sync(
- for (j = 0; j < group_size; j++) {
- struct pipe_ctx *temp;
-
-- if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
-+ if (!pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) {
- if (j == 0)
- break;
-
-@@ -859,7 +859,7 @@ static void program_timing_sync(
-
- /* remove any other unblanked pipes as they have already been synced */
- for (j = j + 1; j < group_size; j++) {
-- if (!pipe_set[j]->tg->funcs->is_blanked(pipe_set[j]->tg)) {
-+ if (!pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg)) {
- group_size--;
- pipe_set[j] = pipe_set[group_size];
- j--;
-diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
-index ca4f1db..21af3bc 100644
---- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
-+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
-@@ -309,7 +309,7 @@ void context_timing_trace(
- || pipe_ctx->pipe_idx == underlay_idx)
- continue;
-
-- pipe_ctx->tg->funcs->get_position(pipe_ctx->tg, &position);
-+ pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position);
- h_pos[i] = position.horizontal_count;
- v_pos[i] = position.vertical_count;
- }
-@@ -320,7 +320,7 @@ void context_timing_trace(
- continue;
-
- TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n",
-- pipe_ctx->tg->inst,
-+ pipe_ctx->stream_res.tg->inst,
- pipe_ctx->stream->timing.h_total,
- pipe_ctx->stream->timing.v_total,
- h_pos[i], v_pos[i]);
-diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
-index 7a2fe2f..2c43edf 100644
---- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
-+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
-@@ -1398,7 +1398,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
- */
- controller_id =
- core_dc->current_context->
-- res_ctx.pipe_ctx[i].tg->inst +
-+ res_ctx.pipe_ctx[i].stream_res.tg->inst +
- 1;
- }
- }
-@@ -1504,7 +1504,7 @@ bool dc_link_setup_psr(struct dc_link *link,
- */
- psr_context->controllerId =
- core_dc->current_context->res_ctx.
-- pipe_ctx[i].tg->inst + 1;
-+ pipe_ctx[i].stream_res.tg->inst + 1;
- break;
- }
- }
-@@ -1879,7 +1879,7 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx)
- }
-
- /* turn off otg test pattern if enable */
-- pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg,
-+ pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
- CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
- COLOR_DEPTH_UNDEFINED);
-
-diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
-index 0c90060..eda2594 100644
---- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
-+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
-@@ -2375,7 +2375,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
- pipe_ctx->stream_res.opp->funcs->
- opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
-
-- pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg,
-+ pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
- controller_test_pattern, color_depth);
- }
- break;
-@@ -2388,7 +2388,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
- pipe_ctx->stream_res.opp->funcs->
- opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);
-
-- pipe_ctx->tg->funcs->set_test_pattern(pipe_ctx->tg,
-+ pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
- CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
- color_depth);
- }
-diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
-index 95278ac..fcfd080 100644
---- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
-+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
-@@ -1011,7 +1011,7 @@ static int acquire_first_split_pipe(
- pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
-
- memset(pipe_ctx, 0, sizeof(*pipe_ctx));
-- pipe_ctx->tg = pool->timing_generators[i];
-+ pipe_ctx->stream_res.tg = pool->timing_generators[i];
- pipe_ctx->plane_res.mi = pool->mis[i];
- pipe_ctx->plane_res.ipp = pool->ipps[i];
- pipe_ctx->plane_res.xfm = pool->transforms[i];
-@@ -1094,7 +1094,7 @@ bool resource_attach_surfaces_to_context(
- free_pipe->plane_state = plane_state;
-
- if (tail_pipe) {
-- free_pipe->tg = tail_pipe->tg;
-+ free_pipe->stream_res.tg = tail_pipe->stream_res.tg;
- free_pipe->stream_res.opp = tail_pipe->stream_res.opp;
- free_pipe->stream_enc = tail_pipe->stream_enc;
- free_pipe->audio = tail_pipe->audio;
-@@ -1241,7 +1241,7 @@ static int acquire_first_free_pipe(
- if (!res_ctx->pipe_ctx[i].stream) {
- struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
-
-- pipe_ctx->tg = pool->timing_generators[i];
-+ pipe_ctx->stream_res.tg = pool->timing_generators[i];
- pipe_ctx->plane_res.mi = pool->mis[i];
- pipe_ctx->plane_res.ipp = pool->ipps[i];
- pipe_ctx->plane_res.xfm = pool->transforms[i];
-@@ -1532,7 +1532,7 @@ enum dc_status resource_map_pool_resources(
- pipe_ctx->audio);
- }
-
-- context->stream_status[i].primary_otg_inst = pipe_ctx->tg->inst;
-+ context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
- }
-
- return DC_OK;
-diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
-index 1058789..2de37fe 100644
---- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
-+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
-@@ -253,7 +253,7 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
- &core_dc->current_context->res_ctx;
-
- for (i = 0; i < MAX_PIPES; i++) {
-- struct timing_generator *tg = res_ctx->pipe_ctx[i].tg;
-+ struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
-
- if (res_ctx->pipe_ctx[i].stream != stream)
- continue;
-@@ -277,7 +277,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
- &core_dc->current_context->res_ctx;
-
- for (i = 0; i < MAX_PIPES; i++) {
-- struct timing_generator *tg = res_ctx->pipe_ctx[i].tg;
-+ struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg;
-
- if (res_ctx->pipe_ctx[i].stream != stream)
- continue;
-diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
-index 8140ff3..4894e17 100644
---- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
-+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
-@@ -53,7 +53,7 @@ void dce_pipe_control_lock(struct core_dc *dc,
- struct dce_hwseq *hws = dc->hwseq;
-
- /* Not lock pipe when blank */
-- if (lock && pipe->tg->funcs->is_blanked(pipe->tg))
-+ if (lock && pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
- return;
-
- val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx],
-diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
-index 0601105..1d7c7fb 100644
---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
-@@ -710,7 +710,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
- */
- uint32_t active_total_with_borders;
- uint32_t early_control = 0;
-- struct timing_generator *tg = pipe_ctx->tg;
-+ struct timing_generator *tg = pipe_ctx->stream_res.tg;
-
- /* TODOFPGA may change to hwss.update_info_frame */
- dce110_update_info_frame(pipe_ctx);
-@@ -967,9 +967,9 @@ static void program_scaler(const struct core_dc *dc,
- pipe_ctx->plane_res.scl_data.lb_params.depth,
- &pipe_ctx->stream->bit_depth_params);
-
-- if (pipe_ctx->tg->funcs->set_overscan_blank_color)
-- pipe_ctx->tg->funcs->set_overscan_blank_color(
-- pipe_ctx->tg,
-+ if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color)
-+ pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
-+ pipe_ctx->stream_res.tg,
- &color);
-
- pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
-@@ -991,15 +991,15 @@ static enum dc_status dce110_prog_pixclk_crtc_otg(
- /* program blank color */
- color_space_to_black_color(dc,
- stream->output_color_space, &black_color);
-- pipe_ctx->tg->funcs->set_blank_color(
-- pipe_ctx->tg,
-+ pipe_ctx->stream_res.tg->funcs->set_blank_color(
-+ pipe_ctx->stream_res.tg,
- &black_color);
-
- /*
- * Must blank CRTC after disabling power gating and before any
- * programming, otherwise CRTC will be hung in bad state
- */
-- pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
-+ pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
-
- if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
- pipe_ctx->clock_source,
-@@ -1009,19 +1009,19 @@ static enum dc_status dce110_prog_pixclk_crtc_otg(
- return DC_ERROR_UNEXPECTED;
- }
-
-- pipe_ctx->tg->funcs->program_timing(
-- pipe_ctx->tg,
-+ pipe_ctx->stream_res.tg->funcs->program_timing(
-+ pipe_ctx->stream_res.tg,
- &stream->timing,
- true);
-
-- pipe_ctx->tg->funcs->set_static_screen_control(
-- pipe_ctx->tg,
-+ pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
-+ pipe_ctx->stream_res.tg,
- 0x182);
- }
-
- if (!pipe_ctx_old->stream) {
-- if (false == pipe_ctx->tg->funcs->enable_crtc(
-- pipe_ctx->tg)) {
-+ if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
-+ pipe_ctx->stream_res.tg)) {
- BREAK_TO_DEBUGGER();
- return DC_ERROR_UNEXPECTED;
- }
-@@ -1073,7 +1073,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
- if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
- pipe_ctx->stream_enc->funcs->setup_stereo_sync(
- pipe_ctx->stream_enc,
-- pipe_ctx->tg->inst,
-+ pipe_ctx->stream_res.tg->inst,
- stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
-
-
-@@ -1359,7 +1359,7 @@ static void set_drr(struct pipe_ctx **pipe_ctx,
- */
-
- for (i = 0; i < num_pipes; i++) {
-- pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, &params);
-+ pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
- }
- }
-
-@@ -1372,7 +1372,7 @@ static void get_position(struct pipe_ctx **pipe_ctx,
- /* TODO: handle pipes > 1
- */
- for (i = 0; i < num_pipes; i++)
-- pipe_ctx[i]->tg->funcs->get_position(pipe_ctx[i]->tg, position);
-+ pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
- }
-
- static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
-@@ -1393,8 +1393,8 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
- #endif
-
- for (i = 0; i < num_pipes; i++)
-- pipe_ctx[i]->tg->funcs->
-- set_static_screen_control(pipe_ctx[i]->tg, value);
-+ pipe_ctx[i]->stream_res.tg->funcs->
-+ set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
- }
-
- /* unit: in_khz before mode set, get pixel clock from context. ASIC register
-@@ -1646,12 +1646,12 @@ static void dce110_reset_hw_ctx_wrap(
- if (!pipe_ctx->stream ||
- pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
- core_link_disable_stream(pipe_ctx_old);
-- pipe_ctx_old->tg->funcs->set_blank(pipe_ctx_old->tg, true);
-- if (!hwss_wait_for_blank_complete(pipe_ctx_old->tg)) {
-+ pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
-+ if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
- dm_error("DC: failed to blank crtc!\n");
- BREAK_TO_DEBUGGER();
- }
-- pipe_ctx_old->tg->funcs->disable_crtc(pipe_ctx_old->tg);
-+ pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
- pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
- pipe_ctx_old->plane_res.mi, dc->current_context->stream_count);
- resource_unreference_clock_source(
-@@ -1984,7 +1984,7 @@ static void program_surface_visibility(const struct core_dc *dc,
- blank_target = true;
-
- dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode);
-- pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, blank_target);
-+ pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
-
- }
-
-@@ -2152,9 +2152,9 @@ void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
-
- plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
- if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
-- pipe_ctx->tg->funcs->is_stereo_left_eye) {
-+ pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
- plane_state->status.is_right_eye =\
-- !pipe_ctx->tg->funcs->is_stereo_left_eye(pipe_ctx->tg);
-+ !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
- }
- }
-
-@@ -2218,28 +2218,28 @@ static void dce110_enable_timing_synchronization(
- * Since HW doesn't care which one, we always assign
- * the 1st one in the group. */
- gsl_params.gsl_group = 0;
-- gsl_params.gsl_master = grouped_pipes[0]->tg->inst;
-+ gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
-
- for (i = 0; i < group_size; i++)
-- grouped_pipes[i]->tg->funcs->setup_global_swap_lock(
-- grouped_pipes[i]->tg, &gsl_params);
-+ grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
-+ grouped_pipes[i]->stream_res.tg, &gsl_params);
-
- /* Reset slave controllers on master VSync */
- DC_SYNC_INFO("GSL: enabling trigger-reset\n");
-
- for (i = 1 /* skip the master */; i < group_size; i++)
-- grouped_pipes[i]->tg->funcs->enable_reset_trigger(
-- grouped_pipes[i]->tg, gsl_params.gsl_group);
-+ grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
-+ grouped_pipes[i]->stream_res.tg, gsl_params.gsl_group);
-
-
-
- for (i = 1 /* skip the master */; i < group_size; i++) {
- DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
-- wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->tg);
-+ wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
- /* Regardless of success of the wait above, remove the reset or
- * the driver will start timing out on Display requests. */
- DC_SYNC_INFO("GSL: disabling trigger-reset.\n");
-- grouped_pipes[i]->tg->funcs->disable_reset_trigger(grouped_pipes[i]->tg);
-+ grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(grouped_pipes[i]->stream_res.tg);
- }
-
-
-@@ -2247,7 +2247,7 @@ static void dce110_enable_timing_synchronization(
- * is that the sync'ed displays will not drift out of sync over time*/
- DC_SYNC_INFO("GSL: Restoring register states.\n");
- for (i = 0; i < group_size; i++)
-- grouped_pipes[i]->tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->tg);
-+ grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
-
- DC_SYNC_INFO("GSL: Set-up complete.\n");
- }
-diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
-index 4b7bce2..94058ee 100644
---- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
-+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
-@@ -1016,7 +1016,7 @@ static struct pipe_ctx *dce110_acquire_underlay(
- if (res_ctx->pipe_ctx[underlay_idx].stream)
- return NULL;
-
-- pipe_ctx->tg = pool->timing_generators[underlay_idx];
-+ pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx];
- pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
- /*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
- pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
-@@ -1040,12 +1040,12 @@ static struct pipe_ctx *dce110_acquire_underlay(
- * need to be enabled
- */
-
-- pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg,
-+ pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg,
- &stream->timing,
- false);
-
-- pipe_ctx->tg->funcs->enable_advanced_request(
-- pipe_ctx->tg,
-+ pipe_ctx->stream_res.tg->funcs->enable_advanced_request(
-+ pipe_ctx->stream_res.tg,
- true,
- &stream->timing);
-
-@@ -1057,8 +1057,8 @@ static struct pipe_ctx *dce110_acquire_underlay(
-
- color_space_to_black_color(dc,
- COLOR_SPACE_YCBCR601, &black_color);
-- pipe_ctx->tg->funcs->set_blank_color(
-- pipe_ctx->tg,
-+ pipe_ctx->stream_res.tg->funcs->set_blank_color(
-+ pipe_ctx->stream_res.tg,
- &black_color);
- }
-
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
-index 2db6b46..99ef0f2 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
-@@ -699,7 +699,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
- /* HW program guide assume display already disable
- * by unplug sequence. OTG assume stop.
- */
-- pipe_ctx->tg->funcs->enable_optc_clock(pipe_ctx->tg, true);
-+ pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
-
- if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
- pipe_ctx->clock_source,
-@@ -708,15 +708,15 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
- BREAK_TO_DEBUGGER();
- return DC_ERROR_UNEXPECTED;
- }
-- pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
-- pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
-- pipe_ctx->tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
-- pipe_ctx->tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
-+ pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
-+ pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
-+ pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
-+ pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
-
-- pipe_ctx->tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
-+ pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
-
-- pipe_ctx->tg->funcs->program_timing(
-- pipe_ctx->tg,
-+ pipe_ctx->stream_res.tg->funcs->program_timing(
-+ pipe_ctx->stream_res.tg,
- &stream->timing,
- true);
-
-@@ -729,7 +729,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
- /* TODO: OPP FMT, ABM. etc. should be done here. */
- /* or FPGA now. instance 0 only. TODO: move to opp.c */
-
-- inst_offset = reg_offsets[pipe_ctx->tg->inst].fmt;
-+ inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
-
- pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
- pipe_ctx->stream_res.opp,
-@@ -739,15 +739,15 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
- /* program otg blank color */
- color_space = stream->output_color_space;
- color_space_to_black_color(dc, color_space, &black_color);
-- pipe_ctx->tg->funcs->set_blank_color(
-- pipe_ctx->tg,
-+ pipe_ctx->stream_res.tg->funcs->set_blank_color(
-+ pipe_ctx->stream_res.tg,
- &black_color);
-
-- pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, true);
-- hwss_wait_for_blank_complete(pipe_ctx->tg);
-+ pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
-+ hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
-
- /* VTG is within DCHUB command block. DCFCLK is always on */
-- if (false == pipe_ctx->tg->funcs->enable_crtc(pipe_ctx->tg)) {
-+ if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
- BREAK_TO_DEBUGGER();
- return DC_ERROR_UNEXPECTED;
- }
-@@ -787,9 +787,9 @@ static void reset_back_end_for_pipe(
- * parent pipe.
- */
- if (pipe_ctx->top_pipe == NULL) {
-- pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg);
-+ pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
-
-- pipe_ctx->tg->funcs->enable_optc_clock(pipe_ctx->tg, false);
-+ pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
- }
-
- if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
-@@ -807,7 +807,7 @@ static void reset_back_end_for_pipe(
- pipe_ctx->stream = NULL;
- dm_logger_write(dc->ctx->logger, LOG_DC,
- "Reset back end for pipe %d, tg:%d\n",
-- pipe_ctx->pipe_idx, pipe_ctx->tg->inst);
-+ pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
- }
-
- /* trigger HW to start disconnect plane from stream on the next vsync */
-@@ -974,7 +974,7 @@ static void reset_hw_ctx_wrap(
- /* Lock*/
- for (i = 0; i < dc->res_pool->pipe_count; i++) {
- struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i];
-- struct timing_generator *tg = cur_pipe_ctx->tg;
-+ struct timing_generator *tg = cur_pipe_ctx->stream_res.tg;
-
- if (cur_pipe_ctx->stream)
- tg->funcs->lock(tg);
-@@ -995,7 +995,7 @@ static void reset_hw_ctx_wrap(
- /* Unlock*/
- for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
- struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i];
-- struct timing_generator *tg = cur_pipe_ctx->tg;
-+ struct timing_generator *tg = cur_pipe_ctx->stream_res.tg;
-
- if (cur_pipe_ctx->stream)
- tg->funcs->unlock(tg);
-@@ -1488,9 +1488,9 @@ static void dcn10_pipe_control_lock(
- verify_allow_pstate_change_high(dc->hwseq);
-
- if (lock)
-- pipe->tg->funcs->lock(pipe->tg);
-+ pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
- else
-- pipe->tg->funcs->unlock(pipe->tg);
-+ pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
-
- if (dc->public.debug.sanity_checks)
- verify_allow_pstate_change_high(dc->hwseq);
-@@ -1545,8 +1545,8 @@ static void dcn10_enable_timing_synchronization(
- DC_SYNC_INFO("Setting up OTG reset trigger\n");
-
- for (i = 1; i < group_size; i++)
-- grouped_pipes[i]->tg->funcs->enable_reset_trigger(
-- grouped_pipes[i]->tg, grouped_pipes[0]->tg->inst);
-+ grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
-+ grouped_pipes[i]->stream_res.tg, grouped_pipes[0]->stream_res.tg->inst);
-
-
- DC_SYNC_INFO("Waiting for trigger\n");
-@@ -1554,10 +1554,10 @@ static void dcn10_enable_timing_synchronization(
- /* Need to get only check 1 pipe for having reset as all the others are
- * synchronized. Look at last pipe programmed to reset.
- */
-- wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->tg);
-+ wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
- for (i = 1; i < group_size; i++)
-- grouped_pipes[i]->tg->funcs->disable_reset_trigger(
-- grouped_pipes[i]->tg);
-+ grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
-+ grouped_pipes[i]->stream_res.tg);
-
- DC_SYNC_INFO("Sync complete\n");
- }
-@@ -1700,7 +1700,7 @@ static void dcn10_power_on_fe(
- HUBP_CLOCK_ENABLE, 1);
-
- /* make sure OPP_PIPE_CLOCK_EN = 1 */
-- REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->tg->inst],
-+ REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
- OPP_PIPE_CLOCK_EN, 1);
- /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/
-
-@@ -1920,7 +1920,7 @@ static void update_dchubp_dpp(
- * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
- * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
- */
-- REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->tg->inst);
-+ REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst);
-
- update_plane_addr(dc, pipe_ctx);
-
-@@ -2012,17 +2012,17 @@ static void program_all_pipe_in_tree(
- verify_allow_pstate_change_high(dc->hwseq);
- }
-
-- pipe_ctx->tg->funcs->lock(pipe_ctx->tg);
-+ pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
-
-- pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
-- pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
-- pipe_ctx->tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
-- pipe_ctx->tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
-- pipe_ctx->tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
-+ pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
-+ pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
-+ pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
-+ pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
-+ pipe_ctx->stream_res.tg->dlg_otg_param.signal = pipe_ctx->stream->signal;
-
-- pipe_ctx->tg->funcs->program_global_sync(
-- pipe_ctx->tg);
-- pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !is_pipe_tree_visible(pipe_ctx));
-+ pipe_ctx->stream_res.tg->funcs->program_global_sync(
-+ pipe_ctx->stream_res.tg);
-+ pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, !is_pipe_tree_visible(pipe_ctx));
- }
-
- if (pipe_ctx->plane_state != NULL) {
-@@ -2098,20 +2098,20 @@ static void dcn10_apply_ctx_for_surface(
- */
-
- if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
-- if (pipe_ctx->plane_res.mi->opp_id != 0xf && pipe_ctx->tg->inst == be_idx) {
-+ if (pipe_ctx->plane_res.mi->opp_id != 0xf && pipe_ctx->stream_res.tg->inst == be_idx) {
- dcn10_power_down_fe(dc, pipe_ctx->pipe_idx);
- /*
- * power down fe will unlock when calling reset, need
- * to lock it back here. Messy, need rework.
- */
-- pipe_ctx->tg->funcs->lock(pipe_ctx->tg);
-+ pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
- }
- }
-
-
- if ((!pipe_ctx->plane_state && old_pipe_ctx->plane_state)
- || (!pipe_ctx->stream && old_pipe_ctx->stream)) {
-- if (old_pipe_ctx->tg->inst != be_idx)
-+ if (old_pipe_ctx->stream_res.tg->inst != be_idx)
- continue;
-
- if (!old_pipe_ctx->top_pipe) {
-@@ -2279,7 +2279,7 @@ static void set_drr(struct pipe_ctx **pipe_ctx,
- * some GSL stuff
- */
- for (i = 0; i < num_pipes; i++) {
-- pipe_ctx[i]->tg->funcs->set_drr(pipe_ctx[i]->tg, &params);
-+ pipe_ctx[i]->stream_res.tg->funcs->set_drr(pipe_ctx[i]->stream_res.tg, &params);
- }
- }
-
-@@ -2292,7 +2292,7 @@ static void get_position(struct pipe_ctx **pipe_ctx,
- /* TODO: handle pipes > 1
- */
- for (i = 0; i < num_pipes; i++)
-- pipe_ctx[i]->tg->funcs->get_position(pipe_ctx[i]->tg, position);
-+ pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
- }
-
- static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
-@@ -2307,8 +2307,8 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
- value |= 0x2;
-
- for (i = 0; i < num_pipes; i++)
-- pipe_ctx[i]->tg->funcs->
-- set_static_screen_control(pipe_ctx[i]->tg, value);
-+ pipe_ctx[i]->stream_res.tg->funcs->
-+ set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
- }
-
- static void set_plane_config(
-@@ -2369,8 +2369,8 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc)
- flags.PROGRAM_STEREO == 1 ? true:false,
- stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false);
-
-- pipe_ctx->tg->funcs->program_stereo(
-- pipe_ctx->tg,
-+ pipe_ctx->stream_res.tg->funcs->program_stereo(
-+ pipe_ctx->stream_res.tg,
- &stream->timing,
- &flags);
-
-@@ -2469,7 +2469,7 @@ static bool dcn10_dummy_display_power_gating(
- void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
- {
- struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-- struct timing_generator *tg = pipe_ctx->tg;
-+ struct timing_generator *tg = pipe_ctx->stream_res.tg;
-
- if (plane_state->ctx->dc->debug.sanity_checks) {
- struct core_dc *dc = DC_TO_CORE(plane_state->ctx->dc);
-@@ -2496,7 +2496,7 @@ void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
- if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
- tg->funcs->is_stereo_left_eye) {
- plane_state->status.is_right_eye =
-- !tg->funcs->is_stereo_left_eye(pipe_ctx->tg);
-+ !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
- }
- }
-
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
-index e15eec3..bb9a42d 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
-+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
-@@ -960,7 +960,7 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
- return false;
-
- idle_pipe->stream = head_pipe->stream;
-- idle_pipe->tg = head_pipe->tg;
-+ idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
- idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
-
- idle_pipe->plane_res.mi = pool->mis[idle_pipe->pipe_idx];
-diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
-index 24a5254..488ade3 100644
---- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
-+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
-@@ -154,6 +154,7 @@ struct resource_pool {
-
- struct stream_resource {
- struct output_pixel_processor *opp;
-+ struct timing_generator *tg;
- };
-
- struct plane_resource {
-@@ -171,8 +172,6 @@ struct pipe_ctx {
- struct plane_resource plane_res;
- struct stream_resource stream_res;
-
-- struct timing_generator *tg;
--
- struct stream_encoder *stream_enc;
- struct display_clock *dis_clk;
- struct clock_source *clock_source;
-diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
-index 52361d1..24e47eb 100644
---- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
-+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
-@@ -214,7 +214,7 @@ bool dce110_vblank_set(
- uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
-
- struct timing_generator *tg =
-- core_dc->current_context->res_ctx.pipe_ctx[pipe_offset].tg;
-+ core_dc->current_context->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
-
- if (enable) {
- if (!tg->funcs->arm_vert_intr(tg, 2)) {
---
-2.7.4
-